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llvm-project/llvm/test/CodeGen/PowerPC/vsx-args.ll

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[PowerPC] v2[fi]64 need to be explicitly passed in VSX registers v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. llvm-svn: 205041
2014-03-29 03:58:11 +08:00
; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
[PowerPC]Update Power VSX test cases to also test fast-isel Update of some of the VSX test cases for Power to check fast-isel codegen as well as the regular codegen. http://reviews.llvm.org/D6357 llvm-svn: 223509
2014-12-06 04:32:05 +08:00
; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck %s
[PowerPC] v2[fi]64 need to be explicitly passed in VSX registers v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. llvm-svn: 205041
2014-03-29 03:58:11 +08:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
entry:
%ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a)
%v = fadd <2 x double> %ca, <double 1.0, double 1.0>
ret <2 x double> %v
; CHECK-LABEL: @main
; CHECK-DAG: vor [[V:[0-9]+]], 2, 2
; CHECK-DAG: xxlor 34, 35, 35
; CHECK-DAG: xxlor 35, 36, 36
; CHECK-DAG: vor 4, [[V]], [[V]]
; CHECK-DAG: bl sv
; CHECK-DAG: lxvd2x [[VC:[0-9]+]],
; CHECK: xvadddp 34, 34, [[VC]]
; CHECK: blr
}
attributes #0 = { noinline nounwind readnone }
attributes #1 = { nounwind }