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llvm-project/llvm/test/CodeGen/X86/vec_extract-mmx.ll

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[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
define i32 @test0(<1 x i64>* %v4) nounwind {
; X32-LABEL: test0:
; X32: # BB#0: # %entry
; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-8, %esp
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: subl $8, %esp
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: movl 8(%ebp), %eax
; X32-NEXT: movl (%eax), %ecx
; X32-NEXT: movl 4(%eax), %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X32-NEXT: movl %ecx, (%esp)
; X32-NEXT: pshufw $238, (%esp), %mm0 # mm0 = mem[2,3,2,3]
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: movd %mm0, %eax
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: addl $32, %eax
; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp
; X32-NEXT: retl
;
; X64-LABEL: test0:
; X64: # BB#0: # %entry
; X64-NEXT: pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3]
; X64-NEXT: movd %mm0, %eax
; X64-NEXT: addl $32, %eax
; X64-NEXT: retq
[X86][MMX] Remove widening experimental flag from MMX tests. Turns out that after the past MMX commits, we don't need to rely on this flag to get better codegen for MMX. Also update the tests to become triple neutral. llvm-svn: 230637
2015-02-26 23:10:38 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%v5 = load <1 x i64>, <1 x i64>* %v4, align 8
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
%v12 = bitcast <1 x i64> %v5 to <4 x i16>
%v13 = bitcast <4 x i16> %v12 to x86_mmx
%v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
%v15 = bitcast x86_mmx %v14 to <4 x i16>
%v16 = bitcast <4 x i16> %v15 to <1 x i64>
%v17 = extractelement <1 x i64> %v16, i32 0
%v18 = bitcast i64 %v17 to <2 x i32>
%v19 = extractelement <2 x i32> %v18, i32 0
%v20 = add i32 %v19, 32
ret i32 %v20
}
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
define i32 @test1(i32* nocapture readonly %ptr) nounwind {
; X32-LABEL: test1:
; X32: # BB#0: # %entry
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: movd (%eax), %mm0
; X32-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: movd %mm0, %eax
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: emms
; X32-NEXT: retl
;
; X64-LABEL: test1:
; X64: # BB#0: # %entry
; X64-NEXT: movd (%rdi), %mm0
; X64-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
; X64-NEXT: movd %mm0, %eax
; X64-NEXT: emms
; X64-NEXT: retq
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %ptr, align 4
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
%1 = insertelement <2 x i32> undef, i32 %0, i32 0
%2 = insertelement <2 x i32> %1, i32 0, i32 1
%3 = bitcast <2 x i32> %2 to x86_mmx
%4 = bitcast x86_mmx %3 to i64
%5 = bitcast i64 %4 to <4 x i16>
%6 = bitcast <4 x i16> %5 to x86_mmx
%7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
%8 = bitcast x86_mmx %7 to <4 x i16>
%9 = bitcast <4 x i16> %8 to <1 x i64>
%10 = extractelement <1 x i64> %9, i32 0
%11 = bitcast i64 %10 to <2 x i32>
%12 = extractelement <2 x i32> %11, i32 0
tail call void @llvm.x86.mmx.emms()
ret i32 %12
}
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
define i32 @test2(i32* nocapture readonly %ptr) nounwind {
; X32-LABEL: test2:
; X32: # BB#0: # %entry
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3]
[X86][MMX] Fixed i32 extraction on 32-bit targets MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
2017-03-03 02:56:06 +08:00
; X32-NEXT: movd %mm0, %eax
[X86][SSE] Regenerated the vec_extract tests. llvm-svn: 265183
2016-04-02 04:55:19 +08:00
; X32-NEXT: emms
; X32-NEXT: retl
;
; X64-LABEL: test2:
; X64: # BB#0: # %entry
; X64-NEXT: pshufw $232, (%rdi), %mm0 # mm0 = mem[0,2,2,3]
; X64-NEXT: movd %mm0, %eax
; X64-NEXT: emms
; X64-NEXT: retq
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
entry:
%0 = bitcast i32* %ptr to x86_mmx*
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%1 = load x86_mmx, x86_mmx* %0, align 8
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
%3 = bitcast x86_mmx %2 to <4 x i16>
%4 = bitcast <4 x i16> %3 to <1 x i64>
%5 = extractelement <1 x i64> %4, i32 0
%6 = bitcast i64 %5 to <2 x i32>
%7 = extractelement <2 x i32> %6, i32 0
tail call void @llvm.x86.mmx.emms()
ret i32 %7
}
[X86] Re-enable MMX i32 extractelt combine. This effectively adds back the extractelt combine removed by r262358: the direct case can still occur (because x86_mmx is special, see r262446), but it's the indirect case that's now superseded by the generic combine. llvm-svn: 267651
2016-04-27 09:35:25 +08:00
define i32 @test3(x86_mmx %a) nounwind {
; X32-LABEL: test3:
; X32: # BB#0:
; X32-NEXT: movd %mm0, %eax
; X32-NEXT: retl
;
; X64-LABEL: test3:
; X64: # BB#0:
; X64-NEXT: movd %mm0, %eax
; X64-NEXT: retq
%tmp0 = bitcast x86_mmx %a to <2 x i32>
%tmp1 = extractelement <2 x i32> %tmp0, i32 0
ret i32 %tmp1
}
[X86] Don't assume that MMX extractelts are from index 0. It's probably the case for all 3 MMX users out there, but with hand-crafted IR, you can trigger selection failures. Fix that. llvm-svn: 267652
2016-04-27 09:35:29 +08:00
; Verify we don't muck with extractelts from the upper lane.
define i32 @test4(x86_mmx %a) nounwind {
; X32-LABEL: test4:
; X32: # BB#0:
; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $8, %esp
; X32-NEXT: movq %mm0, (%esp)
[X86][SSE] Add support for combining target shuffles to SHUFPS. As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point. llvm-svn: 290064
2016-12-18 22:26:02 +08:00
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] Propagate undef upper elements from scalar_to_vector during shuffle combining Only do this for integer types currently - floats types (in particular insertps) load folding often fails with this. llvm-svn: 295208
2017-02-16 01:41:33 +08:00
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
[X86] Don't assume that MMX extractelts are from index 0. It's probably the case for all 3 MMX users out there, but with hand-crafted IR, you can trigger selection failures. Fix that. llvm-svn: 267652
2016-04-27 09:35:29 +08:00
; X32-NEXT: movd %xmm0, %eax
; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp
; X32-NEXT: retl
;
; X64-LABEL: test4:
; X64: # BB#0:
; X64-NEXT: movq %mm0, -{{[0-9]+}}(%rsp)
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,0,1]
; X64-NEXT: movd %xmm0, %eax
; X64-NEXT: retq
%tmp0 = bitcast x86_mmx %a to <2 x i32>
%tmp1 = extractelement <2 x i32> %tmp0, i32 1
ret i32 %tmp1
}
[X86][MMX] Add tests for MMX extract element LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
2015-02-03 06:00:48 +08:00
declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
declare void @llvm.x86.mmx.emms()