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llvm-project/llvm/test/CodeGen/X86/overflow-intrinsic-setcc-fo...

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[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
define i1 @saddo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: saddo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: addl %esi, %edi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @saddo_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: saddo_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: addq %rsi, %rdi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @uaddo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: uaddo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: addl %esi, %edi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setae %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @uaddo_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: uaddo_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: addq %rsi, %rdi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setae %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @ssubo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: ssubo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: cmpl %esi, %edi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @ssub_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: ssub_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: cmpq %rsi, %rdi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @usubo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: usubo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: cmpl %esi, %edi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setae %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @usubo_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: usubo_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: cmpq %rsi, %rdi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setae %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @smulo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: smulo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: imull %esi, %edi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @smulo_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: smulo_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: imulq %rsi, %rdi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @umulo_not_i32(i32 %v1, i32 %v2) {
; CHECK-LABEL: umulo_not_i32:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: mull %esi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%obit = extractvalue {i32, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
define i1 @umulo_not_i64(i64 %v1, i64 %v2) {
; CHECK-LABEL: umulo_not_i64:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: mulq %rsi
[X86] Improve codegen for inverted overflow checking intrinsics. Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val) Differential Revision: https://reviews.llvm.org/D38161 llvm-svn: 314514
2017-09-29 21:53:44 +08:00
; CHECK-NEXT: setno %al
[X86] Add overflow intrinsic test in preparation for D38161. This commit adds the test file before codegen changes as requested in D38161 to make it easier to see the difference. llvm-svn: 314416
2017-09-28 21:43:48 +08:00
; CHECK-NEXT: retq
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%obit = extractvalue {i64, i1} %t, 1
%ret = xor i1 %obit, true
ret i1 %ret
}
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone