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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

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MIRTests: Remove unnecessary 2>&1 redirection llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
2017-02-23 02:47:41 +08:00
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
[GlobalISel] Get the AArch64 tests to work on Linux Mostly this just means changing the triple from aarch64-apple-ios to the generic aarch64--. Only one test needs more significant changes, but GlobalISel already does the right thing so it's ok to just change the checks. Differential Revision: https://reviews.llvm.org/D25532 llvm-svn: 284223
2016-10-14 18:19:40 +08:00
target triple = "aarch64--"
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
define void @test_simple() {
entry:
ret void
GlobalISel: legalize conditional branches on AArch64. llvm-svn: 279565
2016-08-24 05:01:20 +08:00
next:
ret void
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
}
[AArch64][LegalizerInfo] Mark s128 G_BITCAST legal We used to mark all G_BITCAST of 128-bit legal but only for vector types. Scalars of this size are just fine as well. llvm-svn: 315945
2017-10-17 06:28:27 +08:00
define void @bitcast128() {
ret void
}
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
...
---
name: test_simple
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
GlobalISel: legalize conditional branches on AArch64. llvm-svn: 279565
2016-08-24 05:01:20 +08:00
- { id: 3, class: _ }
GlobalISel: mark float/int conversions legal llvm-svn: 279839
2016-08-27 01:45:58 +08:00
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
- { id: 9, class: _ }
- { id: 10, class: _ }
- { id: 11, class: _ }
- { id: 12, class: _ }
- { id: 13, class: _ }
- { id: 14, class: _ }
- { id: 15, class: _ }
- { id: 16, class: _ }
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
2016-09-09 19:46:34 +08:00
%0(s64) = COPY %x0
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%1(s1) = G_TRUNC %0
%2(s8) = G_TRUNC %0
%3(s16) = G_TRUNC %0
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
2016-09-09 19:46:34 +08:00
%4(s32) = G_TRUNC %0
GlobalISel: mark float/int conversions legal llvm-svn: 279839
2016-08-27 01:45:58 +08:00
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
; CHECK-LABEL: name: test_simple
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: %5:_(p0) = G_INTTOPTR %0
; CHECK: %6:_(s64) = G_PTRTOINT %5
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%5(p0) = G_INTTOPTR %0
%6(s64) = G_PTRTOINT %5
GlobalISel: mark float/int conversions legal llvm-svn: 279839
2016-08-27 01:45:58 +08:00
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
; CHECK: G_BRCOND %1(s1), %bb.1.next
G_BRCOND %1, %bb.1.next
GlobalISel: mark float/int conversions legal llvm-svn: 279839
2016-08-27 01:45:58 +08:00
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
bb.1.next:
GlobalISel: mark selects legal llvm-svn: 279840
2016-08-27 01:46:03 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
; CHECK: %7:_(s1) = G_TRUNC [[RES]](s32)
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%7(s1) = G_SELECT %1, %1, %1
GlobalISel: legalize narrow G_SELECTS on AArch64. Otherwise there aren't any patterns to select them. llvm-svn: 294261
2017-02-07 07:41:27 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
; CHECK: %8:_(s8) = G_TRUNC [[RES]](s32)
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%8(s8) = G_SELECT %1, %2, %2
GlobalISel: legalize narrow G_SELECTS on AArch64. Otherwise there aren't any patterns to select them. llvm-svn: 294261
2017-02-07 07:41:27 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
; CHECK: %9:_(s16) = G_TRUNC [[RES]](s32)
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%9(s16) = G_SELECT %1, %3, %3
GlobalISel: legalize narrow G_SELECTS on AArch64. Otherwise there aren't any patterns to select them. llvm-svn: 294261
2017-02-07 07:41:27 +08:00
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%10(s32) = G_SELECT %1, %4, %4
%11(s64) = G_SELECT %1, %0, %0
[AArch64][MachineLegalizer] Mark more bitcasts as legal. Those are copies, we do not have to do any legalization action for them. llvm-svn: 283970
2016-10-12 11:57:43 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: %12:_(<2 x s32>) = G_BITCAST %0
; CHECK: %13:_(s64) = G_BITCAST %12
; CHECK: %14:_(s32) = G_BITCAST %10
; CHECK: %15:_(<4 x s8>) = G_BITCAST %0
; CHECK: %16:_(<2 x s16>) = G_BITCAST %0
[AArch64][GlobalISel] Split FP conversion legalizer tests. NFC. Big functions with large vreg # are quite unwieldy to update. Change it to have one function per test (it does increase boilerplate, but makes the core hopefully more readable and maintanable). llvm-svn: 292552
2017-01-20 08:30:09 +08:00
%12(<2 x s32>) = G_BITCAST %0
%13(s64) = G_BITCAST %12
%14(s32) = G_BITCAST %10
%15(<4 x s8>) = G_BITCAST %0
%16(<2 x s16>) = G_BITCAST %0
GlobalISel: mark pointer casts legal on AArch64. llvm-svn: 279553
2016-08-24 03:30:38 +08:00
...
[AArch64][LegalizerInfo] Mark s128 G_BITCAST legal We used to mark all G_BITCAST of 128-bit legal but only for vector types. Scalars of this size are just fine as well. llvm-svn: 315945
2017-10-17 06:28:27 +08:00
---
name: bitcast128
tracksRegLiveness: true
registers:
- { id: 0, class: _}
- { id: 1, class: _}
- { id: 2, class: _}
- { id: 3, class: _}
body: |
bb.1:
liveins: %x0, %x1
; CHECK-LABEL: bitcast128
; This is legal and shouldn't be changed.
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: %2:_(<2 x s64>) = G_BITCAST %3(s128)
[AArch64][LegalizerInfo] Mark s128 G_BITCAST legal We used to mark all G_BITCAST of 128-bit legal but only for vector types. Scalars of this size are just fine as well. llvm-svn: 315945
2017-10-17 06:28:27 +08:00
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
%2(<2 x s64>) = G_BITCAST %3(s128)
%q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit %q0
...