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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir

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MIRTests: Remove unnecessary 2>&1 redirection llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
2017-02-23 02:47:41 +08:00
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
[GlobalISel] Get the AArch64 tests to work on Linux Mostly this just means changing the triple from aarch64-apple-ios to the generic aarch64--. Only one test needs more significant changes, but GlobalISel already does the right thing so it's ok to just change the checks. Differential Revision: https://reviews.llvm.org/D25532 llvm-svn: 284223
2016-10-14 18:19:40 +08:00
target triple = "aarch64--"
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
define void @test_icmp() {
entry:
ret void
}
...
---
name: test_icmp
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
[GISel]: Support Widening G_ICMP's destination operand. Updated AArch64 to widen destination to s32. https://reviews.llvm.org/D35737 Reviewed by Tim llvm-svn: 309579
2017-08-01 01:00:16 +08:00
- { id: 6, class: _ }
- { id: 7, class: _ }
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
GlobalISel: remove G_TYPE and G_PHI These instructions were only necessary when type information was stored in the MachineInstr (because only generic MachineInstrs possessed a type). Now that it's in MachineRegisterInfo, COPY and PHI work fine. llvm-svn: 281037
2016-09-09 19:47:31 +08:00
%0(s64) = COPY %x0
%1(s64) = COPY %x0
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
2016-09-09 19:46:34 +08:00
%2(s32) = G_TRUNC %0
%3(s32) = G_TRUNC %1
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), %0(s64), %1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
[GISel]: Support Widening G_ICMP's destination operand. Updated AArch64 to widen destination to s32. https://reviews.llvm.org/D35737 Reviewed by Tim llvm-svn: 309579
2017-08-01 01:00:16 +08:00
%4(s32) = G_FCMP floatpred(oge), %0, %1
%6(s1) = G_TRUNC %4(s32)
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), %2(s32), %3
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
[GISel]: Support Widening G_ICMP's destination operand. Updated AArch64 to widen destination to s32. https://reviews.llvm.org/D35737 Reviewed by Tim llvm-svn: 309579
2017-08-01 01:00:16 +08:00
%5(s32) = G_FCMP floatpred(uno), %2, %3
%7(s1) = G_TRUNC %5(s32)
GlobalISel: mark G_FCMP legal on float & double. llvm-svn: 279844
2016-08-27 01:46:19 +08:00
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