2003-10-06 03:27:59 +08:00
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//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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2005-04-22 08:00:37 +08:00
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//
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2003-10-21 04:20:30 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:37:13 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 08:00:37 +08:00
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//
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2003-10-21 04:20:30 +08:00
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//===----------------------------------------------------------------------===//
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2003-10-06 03:27:59 +08:00
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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2004-08-01 12:04:35 +08:00
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#include "CodeGenTarget.h"
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2003-10-06 03:27:59 +08:00
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#include "Record.h"
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2005-11-02 02:04:06 +08:00
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#include <algorithm>
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2007-12-30 08:25:23 +08:00
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#include <iostream>
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2004-08-01 11:55:39 +08:00
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using namespace llvm;
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2003-11-12 06:41:34 +08:00
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2008-01-06 09:21:51 +08:00
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static void PrintDefList(const std::vector<Record*> &Uses,
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unsigned Num, std::ostream &OS) {
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2005-08-19 05:36:47 +08:00
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OS << "static const unsigned ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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2003-10-06 03:27:59 +08:00
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OS << "0 };\n";
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}
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2008-01-06 09:20:13 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary Information.
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//===----------------------------------------------------------------------===//
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struct RecordNameComparator {
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bool operator()(const Record *Rec1, const Record *Rec2) const {
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return Rec1->getName() < Rec2->getName();
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}
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};
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void InstrInfoEmitter::GatherItinClasses() {
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std::vector<Record*> DefList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
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for (unsigned i = 0, N = DefList.size(); i < N; i++)
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ItinClassMap[DefList[i]->getName()] = i;
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}
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unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
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return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
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}
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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2006-11-07 07:49:51 +08:00
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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2006-11-10 10:01:40 +08:00
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2005-08-20 02:46:26 +08:00
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for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
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2006-11-10 10:01:40 +08:00
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CodeGenInstruction::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Inst.OperandList[i]);
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2005-11-19 15:05:57 +08:00
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} else {
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for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
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2006-11-10 10:01:40 +08:00
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OperandList.push_back(Inst.OperandList[i]);
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2006-11-07 07:49:51 +08:00
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2006-11-10 10:01:40 +08:00
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Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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2006-11-07 07:53:31 +08:00
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2006-11-10 10:01:40 +08:00
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else
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Res += "0, ";
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// Fill in applicable flags.
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Res += "0";
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2006-11-07 07:49:51 +08:00
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2006-11-10 10:01:40 +08:00
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// Ptr value whose register class is resolved via callback.
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if (OpR->getName() == "ptr_rc")
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2008-01-07 14:42:05 +08:00
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Res += "|(1<<TOI::LookupPtrRegClass)";
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2006-11-10 10:01:40 +08:00
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOperand.
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2007-07-07 07:23:38 +08:00
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if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
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2008-01-07 14:42:05 +08:00
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Res += "|(1<<TOI::Predicate)";
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2006-11-07 07:49:51 +08:00
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2007-07-11 02:05:01 +08:00
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
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2008-01-07 14:42:05 +08:00
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Res += "|(1<<TOI::OptionalDef)";
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2007-07-11 02:05:01 +08:00
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2006-11-10 10:01:40 +08:00
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// Fill in constraint info.
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2006-11-15 10:38:17 +08:00
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Res += ", " + Inst.OperandList[i].Constraints[j];
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2006-11-10 10:01:40 +08:00
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Result.push_back(Res);
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2005-08-20 02:46:26 +08:00
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}
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}
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2006-11-01 08:27:05 +08:00
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2005-08-20 02:46:26 +08:00
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return Result;
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}
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2008-01-06 09:20:13 +08:00
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void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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N = ++OperandListNum;
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OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
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OS << "{ " << OperandInfo[i] << " }, ";
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OS << "};\n";
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}
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}
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2008-01-06 09:53:37 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction Analysis
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//===----------------------------------------------------------------------===//
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2008-01-06 10:16:26 +08:00
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class InstAnalyzer {
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const CodeGenDAGPatterns &CDP;
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2008-01-06 16:36:04 +08:00
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bool &mayStore;
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2008-01-09 02:05:21 +08:00
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bool &mayLoad;
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2008-01-10 13:39:30 +08:00
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bool &HasSideEffects;
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2008-01-06 10:16:26 +08:00
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public:
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InstAnalyzer(const CodeGenDAGPatterns &cdp,
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2008-01-10 13:39:30 +08:00
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bool &maystore, bool &mayload, bool &hse)
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: CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse){
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2008-01-06 10:16:26 +08:00
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}
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2008-01-10 15:59:24 +08:00
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/// Analyze - Analyze the specified instruction, returning true if the
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/// instruction had a pattern.
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bool Analyze(Record *InstRecord) {
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2008-01-06 10:16:26 +08:00
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const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
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2008-01-10 13:40:54 +08:00
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if (Pattern == 0) {
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HasSideEffects = 1;
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2008-01-10 15:59:24 +08:00
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return false; // No pattern.
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2008-01-10 13:40:54 +08:00
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}
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2008-01-06 10:16:26 +08:00
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// FIXME: Assume only the first tree is the pattern. The others are clobber
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// nodes.
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AnalyzeNode(Pattern->getTree(0));
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2008-01-10 15:59:24 +08:00
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return true;
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2008-01-06 10:16:26 +08:00
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}
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private:
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void AnalyzeNode(const TreePatternNode *N) {
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2008-01-10 15:59:24 +08:00
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if (N->isLeaf()) {
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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Record *LeafRec = DI->getDef();
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// Handle ComplexPattern leaves.
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if (LeafRec->isSubClassOf("ComplexPattern")) {
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const ComplexPattern &CP = CDP.getComplexPattern(LeafRec);
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if (CP.hasProperty(SDNPMayStore)) mayStore = true;
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if (CP.hasProperty(SDNPMayLoad)) mayLoad = true;
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if (CP.hasProperty(SDNPSideEffect)) HasSideEffects = true;
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}
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}
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2008-01-06 10:16:26 +08:00
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return;
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2008-01-10 15:59:24 +08:00
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}
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2008-01-06 10:16:26 +08:00
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2008-01-10 13:39:30 +08:00
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// Analyze children.
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2008-01-06 10:16:26 +08:00
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for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
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AnalyzeNode(N->getChild(i));
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2008-01-10 13:39:30 +08:00
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// Ignore set nodes, which are not SDNodes.
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if (N->getOperator()->getName() == "set")
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return;
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// Get information about the SDNode for the operator.
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const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
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2008-01-10 15:59:24 +08:00
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// Notice properties of the node.
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if (OpInfo.hasProperty(SDNPMayStore)) mayStore = true;
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if (OpInfo.hasProperty(SDNPMayLoad)) mayLoad = true;
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if (OpInfo.hasProperty(SDNPSideEffect)) HasSideEffects = true;
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2008-01-10 13:39:30 +08:00
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if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
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// If this is an intrinsic, analyze it.
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if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem)
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mayLoad = true;// These may load memory.
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if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
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mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
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if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem)
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// WriteMem intrinsics can have other strange effects.
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HasSideEffects = true;
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}
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2008-01-06 10:16:26 +08:00
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}
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};
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2008-01-06 09:53:37 +08:00
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void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
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2008-01-10 13:39:30 +08:00
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bool &MayStore, bool &MayLoad,
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bool &HasSideEffects) {
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MayStore = MayLoad = HasSideEffects = false;
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2008-01-06 09:53:37 +08:00
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2008-01-10 15:59:24 +08:00
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bool HadPattern =
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InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects).Analyze(Inst.TheDef);
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2008-01-06 14:44:58 +08:00
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2008-01-10 12:44:48 +08:00
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// InstAnalyzer only correctly analyzes mayStore/mayLoad so far.
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2008-01-06 16:36:04 +08:00
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if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
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2008-01-06 14:44:58 +08:00
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// If we decided that this is a store from the pattern, then the .td file
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// entry is redundant.
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2008-01-10 13:39:30 +08:00
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if (MayStore)
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2008-01-06 16:36:04 +08:00
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fprintf(stderr,
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"Warning: mayStore flag explicitly set on instruction '%s'"
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2008-01-06 14:44:58 +08:00
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" but flag already inferred from pattern.\n",
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2008-01-07 12:57:31 +08:00
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Inst.TheDef->getName().c_str());
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2008-01-10 13:39:30 +08:00
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MayStore = true;
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2008-01-06 14:44:58 +08:00
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}
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2008-01-10 12:44:48 +08:00
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if (Inst.mayLoad) { // If the .td file explicitly sets mayLoad, use it.
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// If we decided that this is a load from the pattern, then the .td file
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// entry is redundant.
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2008-01-10 13:39:30 +08:00
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if (MayLoad)
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2008-01-10 12:44:48 +08:00
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fprintf(stderr,
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"Warning: mayLoad flag explicitly set on instruction '%s'"
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" but flag already inferred from pattern.\n",
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Inst.TheDef->getName().c_str());
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2008-01-10 13:39:30 +08:00
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MayLoad = true;
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2008-01-10 12:44:48 +08:00
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}
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2008-01-10 13:39:30 +08:00
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if (Inst.neverHasSideEffects) {
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2008-01-10 15:59:24 +08:00
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if (HadPattern)
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fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
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"which already has a pattern\n", Inst.TheDef->getName().c_str());
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2008-01-10 13:39:30 +08:00
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HasSideEffects = false;
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}
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2008-01-10 15:59:24 +08:00
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if (Inst.hasSideEffects) {
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if (HasSideEffects)
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fprintf(stderr, "Warning: hasSideEffects set on instruction '%s' "
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"which already inferred this.\n", Inst.TheDef->getName().c_str());
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HasSideEffects = true;
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}
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2008-01-06 09:53:37 +08:00
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}
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2008-01-06 09:20:13 +08:00
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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2003-10-06 03:27:59 +08:00
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(std::ostream &OS) {
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2005-11-01 01:16:46 +08:00
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GatherItinClasses();
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2003-10-06 03:27:59 +08:00
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EmitSourceFileHeader("Target Instruction Descriptors", OS);
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2004-08-17 11:08:28 +08:00
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OS << "namespace llvm {\n\n";
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2003-10-06 03:27:59 +08:00
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CodeGenTarget Target;
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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2005-08-19 05:36:47 +08:00
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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// Emit all of the instruction's implicit uses and defs.
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2004-08-01 13:04:00 +08:00
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = II->second.TheDef;
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2005-10-29 06:59:53 +08:00
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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2005-08-19 05:36:47 +08:00
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unsigned &IL = EmittedLists[Uses];
|
2008-01-06 09:21:51 +08:00
|
|
|
if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
|
2005-08-19 05:36:47 +08:00
|
|
|
}
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
|
|
|
|
if (!Defs.empty()) {
|
|
|
|
unsigned &IL = EmittedLists[Defs];
|
2008-01-06 09:21:51 +08:00
|
|
|
if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
|
2005-08-19 05:36:47 +08:00
|
|
|
}
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
|
|
|
|
2008-01-06 09:20:13 +08:00
|
|
|
OperandInfoMapTy OperandInfoIDs;
|
2005-08-20 02:46:26 +08:00
|
|
|
|
2005-08-20 00:57:28 +08:00
|
|
|
// Emit all of the operand info records.
|
2008-01-06 09:20:13 +08:00
|
|
|
EmitOperandInfo(OS, OperandInfoIDs);
|
2005-08-20 00:57:28 +08:00
|
|
|
|
2008-01-07 15:27:27 +08:00
|
|
|
// Emit all of the TargetInstrDesc records in their ENUM ordering.
|
2005-08-20 00:57:28 +08:00
|
|
|
//
|
2008-01-07 15:27:27 +08:00
|
|
|
OS << "\nstatic const TargetInstrDesc " << TargetName
|
2003-10-06 03:27:59 +08:00
|
|
|
<< "Insts[] = {\n";
|
2006-01-27 09:44:09 +08:00
|
|
|
std::vector<const CodeGenInstruction*> NumberedInstructions;
|
|
|
|
Target.getInstructionsByEnumValue(NumberedInstructions);
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2006-01-27 09:44:09 +08:00
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
|
|
|
|
emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
|
2008-01-06 09:20:13 +08:00
|
|
|
OperandInfoIDs, OS);
|
2003-10-06 03:27:59 +08:00
|
|
|
OS << "};\n";
|
2004-08-17 11:08:28 +08:00
|
|
|
OS << "} // End llvm namespace \n";
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
|
|
|
|
2004-08-01 13:04:00 +08:00
|
|
|
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
2005-08-19 05:36:47 +08:00
|
|
|
Record *InstrInfo,
|
2005-10-29 06:59:53 +08:00
|
|
|
std::map<std::vector<Record*>, unsigned> &EmittedLists,
|
2008-01-06 09:20:13 +08:00
|
|
|
const OperandInfoMapTy &OpInfo,
|
2005-08-19 05:36:47 +08:00
|
|
|
std::ostream &OS) {
|
2008-01-06 09:53:37 +08:00
|
|
|
// Determine properties of the instruction from its pattern.
|
2008-01-10 13:39:30 +08:00
|
|
|
bool mayStore, mayLoad, HasSideEffects;
|
|
|
|
InferFromPattern(Inst, mayStore, mayLoad, HasSideEffects);
|
2008-01-06 09:53:37 +08:00
|
|
|
|
|
|
|
int MinOperands = 0;
|
2006-06-15 15:22:16 +08:00
|
|
|
if (!Inst.OperandList.empty())
|
2005-08-19 08:59:49 +08:00
|
|
|
// Each logical operand can be multiple MI operands.
|
2006-06-15 15:22:16 +08:00
|
|
|
MinOperands = Inst.OperandList.back().MIOperandNo +
|
2005-08-19 08:59:49 +08:00
|
|
|
Inst.OperandList.back().MINumOperands;
|
|
|
|
|
2006-11-17 09:46:27 +08:00
|
|
|
OS << " { ";
|
2007-08-02 08:20:17 +08:00
|
|
|
OS << Num << ",\t" << MinOperands << ",\t"
|
2008-01-07 13:06:49 +08:00
|
|
|
<< Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
|
|
|
|
<< ",\t\"" << Inst.TheDef->getName() << "\", 0";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
|
|
|
// Emit all of the target indepedent flags...
|
2008-01-07 14:42:05 +08:00
|
|
|
if (Inst.isReturn) OS << "|(1<<TID::Return)";
|
|
|
|
if (Inst.isBranch) OS << "|(1<<TID::Branch)";
|
|
|
|
if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
|
|
|
|
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
|
|
|
|
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
|
|
|
|
if (Inst.isCall) OS << "|(1<<TID::Call)";
|
2008-01-09 02:05:21 +08:00
|
|
|
if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
|
|
|
|
if (mayLoad) OS << "|(1<<TID::MayLoad)";
|
2008-01-07 14:42:05 +08:00
|
|
|
if (mayStore) OS << "|(1<<TID::MayStore)";
|
|
|
|
if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
|
|
|
|
if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
|
|
|
|
if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
|
|
|
|
if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
|
|
|
|
if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
|
|
|
|
if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
|
|
|
|
if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
|
|
|
|
if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
|
2005-08-27 04:42:52 +08:00
|
|
|
if (Inst.usesCustomDAGSchedInserter)
|
2008-01-07 14:42:05 +08:00
|
|
|
OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
|
|
|
|
if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
|
2008-01-11 07:08:24 +08:00
|
|
|
if (HasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
|
2003-10-06 03:27:59 +08:00
|
|
|
OS << ", 0";
|
|
|
|
|
|
|
|
// Emit all of the target-specific flags...
|
|
|
|
ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
|
|
|
|
ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
|
|
|
|
if (LI->getSize() != Shift->getSize())
|
|
|
|
throw "Lengths of " + InstrInfo->getName() +
|
|
|
|
":(TargetInfoFields, TargetInfoPositions) must be equal!";
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
|
2004-08-01 13:04:00 +08:00
|
|
|
emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
|
2003-10-06 03:27:59 +08:00
|
|
|
dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
|
|
|
|
|
|
|
|
OS << ", ";
|
|
|
|
|
|
|
|
// Emit the implicit uses and defs lists...
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
|
|
|
|
if (UseList.empty())
|
2006-07-22 05:15:20 +08:00
|
|
|
OS << "NULL, ";
|
2005-04-22 08:00:37 +08:00
|
|
|
else
|
2005-10-29 06:59:53 +08:00
|
|
|
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2005-10-29 06:59:53 +08:00
|
|
|
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
|
|
|
if (DefList.empty())
|
2006-07-22 05:15:20 +08:00
|
|
|
OS << "NULL, ";
|
2005-04-22 08:00:37 +08:00
|
|
|
else
|
2005-10-29 06:59:53 +08:00
|
|
|
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2005-08-20 00:57:28 +08:00
|
|
|
// Emit the operand info.
|
2006-11-07 07:49:51 +08:00
|
|
|
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
|
2005-08-20 02:46:26 +08:00
|
|
|
if (OperandInfo.empty())
|
|
|
|
OS << "0";
|
2005-08-20 00:57:28 +08:00
|
|
|
else
|
2008-01-06 09:20:13 +08:00
|
|
|
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
2005-08-20 00:57:28 +08:00
|
|
|
|
2004-08-01 13:04:00 +08:00
|
|
|
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
|
|
|
|
2005-11-01 01:16:46 +08:00
|
|
|
|
2003-10-06 03:27:59 +08:00
|
|
|
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
|
|
|
|
IntInit *ShiftInt, std::ostream &OS) {
|
|
|
|
if (Val == 0 || ShiftInt == 0)
|
|
|
|
throw std::string("Illegal value or shift amount in TargetInfo*!");
|
|
|
|
RecordVal *RV = R->getValue(Val->getValue());
|
|
|
|
int Shift = ShiftInt->getValue();
|
|
|
|
|
2006-01-27 09:44:09 +08:00
|
|
|
if (RV == 0 || RV->getValue() == 0) {
|
|
|
|
// This isn't an error if this is a builtin instruction.
|
2007-01-27 01:29:20 +08:00
|
|
|
if (R->getName() != "PHI" &&
|
|
|
|
R->getName() != "INLINEASM" &&
|
2007-07-26 15:48:21 +08:00
|
|
|
R->getName() != "LABEL" &&
|
|
|
|
R->getName() != "EXTRACT_SUBREG" &&
|
|
|
|
R->getName() != "INSERT_SUBREG")
|
2006-01-27 09:44:09 +08:00
|
|
|
throw R->getName() + " doesn't have a field named '" +
|
|
|
|
Val->getValue() + "'!";
|
|
|
|
return;
|
|
|
|
}
|
2003-10-06 03:27:59 +08:00
|
|
|
|
|
|
|
Init *Value = RV->getValue();
|
|
|
|
if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
|
|
|
|
if (BI->getValue()) OS << "|(1<<" << Shift << ")";
|
|
|
|
return;
|
|
|
|
} else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
|
|
|
|
// Convert the Bits to an integer to print...
|
|
|
|
Init *I = BI->convertInitializerTo(new IntRecTy());
|
|
|
|
if (I)
|
|
|
|
if (IntInit *II = dynamic_cast<IntInit*>(I)) {
|
2006-01-27 09:44:09 +08:00
|
|
|
if (II->getValue()) {
|
|
|
|
if (Shift)
|
|
|
|
OS << "|(" << II->getValue() << "<<" << Shift << ")";
|
|
|
|
else
|
|
|
|
OS << "|" << II->getValue();
|
|
|
|
}
|
2003-10-06 03:27:59 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
|
2006-01-27 09:44:09 +08:00
|
|
|
if (II->getValue()) {
|
|
|
|
if (Shift)
|
|
|
|
OS << "|(" << II->getValue() << "<<" << Shift << ")";
|
|
|
|
else
|
|
|
|
OS << II->getValue();
|
|
|
|
}
|
2003-10-06 03:27:59 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-12-30 08:25:23 +08:00
|
|
|
std::cerr << "Unhandled initializer: " << *Val << "\n";
|
2003-10-06 03:27:59 +08:00
|
|
|
throw "In record '" + R->getName() + "' for TSFlag emission.";
|
|
|
|
}
|
2003-11-12 06:41:34 +08:00
|
|
|
|