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llvm-project/lld/test/ELF/ppc32-tls-gd.s

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Fixing ppc tests: sed -i 's/# REQUIES: ppc/# REQUIRES: ppc/g' llvm-svn: 362728
2019-06-07 02:05:10 +08:00
# REQUIRES: ppc
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
# RUN: echo '.tbss; .globl b, c; b: .zero 4; c:' | llvm-mc -filetype=obj -triple=powerpc - -o %t1.o
# RUN: ld.lld -shared -soname=t1.so %t1.o -o %t1.so
# RUN: echo '.globl __tls_get_addr; __tls_get_addr:' | llvm-mc -filetype=obj -triple=powerpc - -o %tga.o
# RUN: ld.lld -shared %t.o %t1.o -o %t.so
# RUN: llvm-readobj -d %t.so | FileCheck --check-prefix=GD-DYN %s
# RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=GD-REL %s
# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck --check-prefix=GD %s
# RUN: ld.lld %t.o %t1.o %tga.o -o %t
# RUN: llvm-readelf -r %t | FileCheck --check-prefix=NOREL %s
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=LE %s
# RUN: ld.lld %t.o %t1.so -o %t
# RUN: llvm-readobj -r %t | FileCheck --check-prefix=IE-REL %s
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=IE %s
## DT_PPC_GOT represents the address of _GLOBAL_OFFSET_TABLE_.
[ELF] Rename .plt to .iplt and decrease EM_PPC{,64} alignment of .glink to 4 GNU ld creates the synthetic section .iplt, and has a built-in linker script that assigns .iplt to the output section .plt . There is no output section named .iplt . Making .iplt an output section actually has a benefit that makes the tricky toolchain feature stand out. Symbolizers don't have to deal with mixed PLT entries (e.g. llvm-objdump -d incorrectly annotates such jump targets). On EM_PPC{,64}, .glink contains a PLT resolver and a series of jump instructions. The 4-byte entry size makes it unnecessary to have an alignment of 16. Mark ppc32-gnu-ifunc.s and ppc32-gnu-ifunc-nonpreemptable.s as `XFAIL: *`. They test IPLT on EM_PPC, which never works. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D71520
2019-12-15 08:19:03 +08:00
# GD-DYN: PPC_GOT 0x20358
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# GD-REL: .rela.dyn {
[ELF] Rename .plt to .iplt and decrease EM_PPC{,64} alignment of .glink to 4 GNU ld creates the synthetic section .iplt, and has a built-in linker script that assigns .iplt to the output section .plt . There is no output section named .iplt . Making .iplt an output section actually has a benefit that makes the tricky toolchain feature stand out. Symbolizers don't have to deal with mixed PLT entries (e.g. llvm-objdump -d incorrectly annotates such jump targets). On EM_PPC{,64}, .glink contains a PLT resolver and a series of jump instructions. The 4-byte entry size makes it unnecessary to have an alignment of 16. Mark ppc32-gnu-ifunc.s and ppc32-gnu-ifunc-nonpreemptable.s as `XFAIL: *`. They test IPLT on EM_PPC, which never works. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D71520
2019-12-15 08:19:03 +08:00
# GD-REL-NEXT: 0x20358 R_PPC_DTPMOD32 a 0x0
# GD-REL-NEXT: 0x2035C R_PPC_DTPREL32 a 0x0
# GD-REL-NEXT: 0x20360 R_PPC_DTPMOD32 b 0x0
# GD-REL-NEXT: 0x20364 R_PPC_DTPREL32 b 0x0
# GD-REL-NEXT: 0x20368 R_PPC_DTPMOD32 c 0x0
# GD-REL-NEXT: 0x2036C R_PPC_DTPREL32 c 0x0
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# GD-REL-NEXT: }
## &DTPMOD(a) - _GLOBAL_OFFSET_TABLE_ = 0x20078 - 0x20078 = 0
# GD: addi 3, 31, 0
[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form ``` // llvm-objdump -d output (before) 0: bl .-4 4: bl .+0 8: bl .+4 // llvm-objdump -d output (after) ; GNU objdump -d 0: bl 0xfffffffc / bl 0xfffffffffffffffc 4: bl 0x4 8: bl 0xc ``` Many Operand's are not annotated as OPERAND_PCREL. They are not affected (e.g. `b .+67108860`). I plan to fix them in future patches. Modified test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s to test address space wraparound for powerpc32 and powerpc64. Reviewed By: sfertile, jhenderson Differential Revision: https://reviews.llvm.org/D76591
2020-03-23 14:03:09 +08:00
# GD-NEXT: bl 0x1028c
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# GD-NEXT: lwz 3, 0(3)
## &DTPMOD(b) - _GLOBAL_OFFSET_TABLE_ = 0x20080 - 0x20078 = 8
# GD-NEXT: addi 3, 31, 8
[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form ``` // llvm-objdump -d output (before) 0: bl .-4 4: bl .+0 8: bl .+4 // llvm-objdump -d output (after) ; GNU objdump -d 0: bl 0xfffffffc / bl 0xfffffffffffffffc 4: bl 0x4 8: bl 0xc ``` Many Operand's are not annotated as OPERAND_PCREL. They are not affected (e.g. `b .+67108860`). I plan to fix them in future patches. Modified test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s to test address space wraparound for powerpc32 and powerpc64. Reviewed By: sfertile, jhenderson Differential Revision: https://reviews.llvm.org/D76591
2020-03-23 14:03:09 +08:00
# GD-NEXT: bl 0x1028c
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# GD-NEXT: lwz 3, 0(3)
## &DTPMOD(c) - _GLOBAL_OFFSET_TABLE_ = 0x20088 - 0x20078 = 16
# GD-NEXT: addi 3, 9, 16
[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form ``` // llvm-objdump -d output (before) 0: bl .-4 4: bl .+0 8: bl .+4 // llvm-objdump -d output (after) ; GNU objdump -d 0: bl 0xfffffffc / bl 0xfffffffffffffffc 4: bl 0x4 8: bl 0xc ``` Many Operand's are not annotated as OPERAND_PCREL. They are not affected (e.g. `b .+67108860`). I plan to fix them in future patches. Modified test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s to test address space wraparound for powerpc32 and powerpc64. Reviewed By: sfertile, jhenderson Differential Revision: https://reviews.llvm.org/D76591
2020-03-23 14:03:09 +08:00
# GD-NEXT: bl 0x1028c
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# GD-NEXT: lwz 3, 0(3)
# NOREL: no relocations
## a@tprel = 8-0x7000 = -28664
# LE: addis 3, 2, 0
# LE-NEXT: addi 3, 3, -28664
# LE-NEXT: lwz 3, 0(3)
## b@tprel = 12-0x7000 = -28660
# LE-NEXT: addis 3, 2, 0
# LE-NEXT: addi 3, 3, -28660
# LE-NEXT: lwz 3, 0(3)
## c@tprel = 16-0x7000 = -28656
# LE-NEXT: addis 3, 2, 0
# LE-NEXT: addi 3, 3, -28656
# LE-NEXT: lwz 3, 0(3)
# IE-REL: .rela.dyn {
[ELF][PPC] Allow PT_LOAD to have overlapping p_offset ranges on EM_PPC Ported the D64906 technique to EM_PPC. Delete ppc-rela.s that is covered by ppc32-abs-pic.s llvm-svn: 369351
2019-08-20 17:20:05 +08:00
# IE-REL-NEXT: 0x10020274 R_PPC_TPREL32 b 0x0
# IE-REL-NEXT: 0x10020278 R_PPC_TPREL32 c 0x0
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D62940 llvm-svn: 362722
2019-06-07 01:03:10 +08:00
# IE-REL-NEXT: }
## a is relaxed to use LE.
## a@tprel = st_value(a)-0x8000 = -28664
# IE: addis 3, 2, 0
# IE-NEXT: addi 3, 3, -28664
# IE-NEXT: lwz 3, 0(3)
## &.got[0] - _GLOBAL_OFFSET_TABLE_ = 0
# IE-NEXT: lwz 3, 0(31)
# IE-NEXT: add 3, 3, 2
# IE-NEXT: lwz 3, 0(3)
## &.got[1] - _GLOBAL_OFFSET_TABLE_ = 4
# IE-NEXT: lwz 3, 4(9)
# IE-NEXT: add 3, 3, 2
# IE-NEXT: lwz 3, 0(3)
addi 3, 31, a@got@tlsgd
bl __tls_get_addr(a@tlsgd)
lwz 3, 0(3)
addi 3, 31, b@got@tlsgd
bl __tls_get_addr(b@tlsgd)
lwz 3, 0(3)
## -fpic may use a different register (e.g. r9).
addi 3, 9, c@got@tlsgd
bl __tls_get_addr(c@tlsgd)
lwz 3, 0(3)
.section .tbss
.globl a
.zero 8
a:
.zero 4