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llvm-project/llvm/test/CodeGen/ARM/atomic-op.ll

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[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7
; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2
LegalizeDAG: allow libcalls for max/min atomic operations ARM processors without ldrex/strex need to be able to make libcalls for all atomic operations, including the newer min/max versions. The alternative would probably be expanding these operations in terms of cmpxchg (as x86 does always), but in the configurations where this matters code-size tends to be paramount so the libcall is more desirable. llvm-svn: 193398
2013-10-25 17:30:20 +08:00
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1-M0
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
ARM: allow misaligned local variables in Thumb1 mode. There's no hard requirement on LLVM to align local variable to 32-bits, so the Thumb1 frame handling needs to be able to deal with variables that are only naturally aligned without falling over. llvm-svn: 219733
2014-10-15 06:12:14 +08:00
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
define void @func(i32 %argc, i8** %argv) nounwind {
entry:
%argc.addr = alloca i32 ; <i32*> [#uses=1]
%argv.addr = alloca i8** ; <i8***> [#uses=1]
%val1 = alloca i32 ; <i32*> [#uses=2]
%val2 = alloca i32 ; <i32*> [#uses=15]
%andt = alloca i32 ; <i32*> [#uses=2]
%ort = alloca i32 ; <i32*> [#uses=2]
%xort = alloca i32 ; <i32*> [#uses=2]
%old = alloca i32 ; <i32*> [#uses=18]
%temp = alloca i32 ; <i32*> [#uses=2]
store i32 %argc, i32* %argc.addr
store i8** %argv, i8*** %argv.addr
store i32 0, i32* %val1
store i32 31, i32* %val2
store i32 3855, i32* %andt
store i32 3855, i32* %ort
store i32 3855, i32* %xort
store i32 4, i32* %temp
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load i32, i32* %temp
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
; CHECK: ldrex
; CHECK: add
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_add_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_add_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %0, i32* %old
; CHECK: ldrex
; CHECK: sub
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_sub_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_sub_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%1 = atomicrmw sub i32* %val2, i32 30 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %1, i32* %old
; CHECK: ldrex
; CHECK: add
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_add_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_add_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%2 = atomicrmw add i32* %val2, i32 1 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %2, i32* %old
; CHECK: ldrex
; CHECK: sub
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_sub_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_sub_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%3 = atomicrmw sub i32* %val2, i32 1 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %3, i32* %old
; CHECK: ldrex
; CHECK: and
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_and_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_and_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: and
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%4 = atomicrmw and i32* %andt, i32 4080 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %4, i32* %old
; CHECK: ldrex
; CHECK: or
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_or_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_or_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: or
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%5 = atomicrmw or i32* %ort, i32 4080 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %5, i32* %old
; CHECK: ldrex
; CHECK: eor
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_xor_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_xor_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: eor
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %6, i32* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_min_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_min_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%7 = atomicrmw min i32* %val2, i32 16 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %7, i32* %old
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
%neg = sub i32 0, 1
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_min_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_min_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%8 = atomicrmw min i32* %val2, i32 %neg monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %8, i32* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_max_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_max_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%9 = atomicrmw max i32* %val2, i32 1 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %9, i32* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_max_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_max_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%10 = atomicrmw max i32* %val2, i32 0 monotonic
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
store i32 %10, i32* %old
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
%11 = atomicrmw umin i32* %val2, i32 16 monotonic
store i32 %11, i32* %old
%uneg = sub i32 0, 1
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
%12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
store i32 %12, i32* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
%13 = atomicrmw umax i32* %val2, i32 1 monotonic
store i32 %13, i32* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_4
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell. llvm-svn: 147032
2011-12-21 11:04:10 +08:00
%14 = atomicrmw umax i32* %val2, i32 0 monotonic
store i32 %14, i32* %old
ret void
Fix the remaining atomic intrinsics to use the right register classes on Thumb2, and add some basic tests for them. llvm-svn: 132235
2011-05-28 07:54:00 +08:00
}
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
define void @func2() nounwind {
entry:
%val = alloca i16
%old = alloca i16
store i16 31, i16* %val
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_2
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_2
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%0 = atomicrmw umin i16* %val, i16 16 monotonic
store i16 %0, i16* %old
%uneg = sub i16 0, 1
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_2
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_2
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%1 = atomicrmw umin i16* %val, i16 %uneg monotonic
store i16 %1, i16* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_2
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_2
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%2 = atomicrmw umax i16* %val, i16 1 monotonic
store i16 %2, i16* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_2
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_2
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%3 = atomicrmw umax i16* %val, i16 0 monotonic
store i16 %3, i16* %old
ret void
}
define void @func3() nounwind {
entry:
%val = alloca i8
%old = alloca i8
store i8 31, i8* %val
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_1
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_1
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%0 = atomicrmw umin i8* %val, i8 16 monotonic
store i8 %0, i8* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umin_1
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umin_1
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%uneg = sub i8 0, 1
%1 = atomicrmw umin i8* %val, i8 %uneg monotonic
store i8 %1, i8* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_1
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_1
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%2 = atomicrmw umax i8* %val, i8 1 monotonic
store i8 %2, i8* %old
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: bl ___sync_fetch_and_umax_1
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: bl ___sync_fetch_and_umax_1
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
Fix a couple of copy-n-paste bugs. Noticed by George Russell! llvm-svn: 147064
2011-12-22 02:56:22 +08:00
%3 = atomicrmw umax i8* %val, i8 0 monotonic
store i8 %3, i8* %old
ret void
}
Fix a couple of typos in EmitAtomic. Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
2012-08-31 10:08:34 +08:00
; CHECK: func4
; This function should not need to use callee-saved registers.
; rdar://problem/12203728
; CHECK-NOT: r4
define i32 @func4(i32* %p) nounwind optsize ssp {
entry:
%0 = atomicrmw add i32* %p, i32 1 monotonic
ret i32 %0
}
ARM: skip cmpxchg failure barrier if ordering is monotonic. The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
2014-04-03 21:06:54 +08:00
define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_fail_order:
IR: add "cmpxchg weak" variant to support permitted failure. This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
2014-06-13 22:24:07 +08:00
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-ARMV7: cmp [[OLDVAL]], r1
; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
ARM: sink atomic release barrier as far as possible into cmpxchg. DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
2016-02-23 04:55:50 +08:00
; CHECK-ARMV7: dmb ish
; CHECK-ARMV7: [[LOOP_BB:\.?LBB.*]]:
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK-ARMV7: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
; CHECK-ARMV7: cmp [[SUCCESS]], #0
ARM: sink atomic release barrier as far as possible into cmpxchg. DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
2016-02-23 04:55:50 +08:00
; CHECK-ARMV7: beq [[SUCCESS_BB:\.?LBB.*]]
; CHECK-ARMV7: ldrex [[OLDVAL]], [r[[ADDR]]]
; CHECK-ARMV7: cmp [[OLDVAL]], r1
; CHECK-ARMV7: beq [[LOOP_BB]]
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK-ARMV7: [[FAIL_BB]]:
; CHECK-ARMV7: clrex
; CHECK-ARMV7: bx lr
ARM: sink atomic release barrier as far as possible into cmpxchg. DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
2016-02-23 04:55:50 +08:00
; CHECK-ARMV7: [[SUCCESS_BB]]:
; CHECK-ARMV7: dmb ish
; CHECK-ARMV7: bx lr
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-T2: cmp [[OLDVAL]], r1
ARM: sink atomic release barrier as far as possible into cmpxchg. DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
2016-02-23 04:55:50 +08:00
; CHECK-T2: bne [[FAIL_BB:\.?LBB.*]]
; CHECK-T2: dmb ish
; CHECK-T2: [[LOOP_BB:\.?LBB.*]]:
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK-T2: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
; CHECK-T2: cmp [[SUCCESS]], #0
; CHECK-T2: dmbeq ish
; CHECK-T2: bxeq lr
ARM: sink atomic release barrier as far as possible into cmpxchg. DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
2016-02-23 04:55:50 +08:00
; CHECK-T2: ldrex [[OLDVAL]], [r[[ADDR]]]
; CHECK-T2: cmp [[OLDVAL]], r1
; CHECK-T2: beq [[LOOP_BB]]
; CHECK-T2: clrex
ARM: skip cmpxchg failure barrier if ordering is monotonic. The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
2014-04-03 21:06:54 +08:00
ret i32 %oldval
}
define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) {
; CHECK-LABEL: test_cmpxchg_fail_order1:
IR: add "cmpxchg weak" variant to support permitted failure. This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
2014-06-13 22:24:07 +08:00
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new acquire acquire
%oldval = extractvalue { i32, i1 } %pair, 0
ARM: skip cmpxchg failure barrier if ordering is monotonic. The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
2014-04-03 21:06:54 +08:00
; CHECK-NOT: dmb ish
; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]:
; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK: cmp [[OLDVAL]], r1
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
ARM: skip cmpxchg failure barrier if ordering is monotonic. The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
2014-04-03 21:06:54 +08:00
; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
; CHECK: cmp [[SUCCESS]], #0
; CHECK: bne [[LOOP_BB]]
[ARM] Emit clrex in the expanded cmpxchg fail block. ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
2015-09-23 01:22:58 +08:00
; CHECK: b [[END_BB:\.?LBB[0-9]+_[0-9]+]]
; CHECK: [[FAIL_BB]]:
; CHECK-NEXT: clrex
; CHECK-NEXT: [[END_BB]]:
ARM: skip cmpxchg failure barrier if ordering is monotonic. The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
2014-04-03 21:06:54 +08:00
; CHECK: dmb ish
; CHECK: bx lr
ret i32 %oldval
}
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
; CHECK-LABEL: load_load_add_acquire
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val1 = load atomic i32, i32* %mem1 acquire, align 4
%val2 = load atomic i32, i32* %mem2 acquire, align 4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
%tmp = add i32 %val1, %val2
; CHECK: ldr {{r[0-9]}}, [r0]
; CHECK: dmb
; CHECK: ldr {{r[0-9]}}, [r1]
; CHECK: dmb
; CHECK: add r0,
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: ldr {{r[0-9]}}, [r0]
; CHECK-T1-M0: dmb
; CHECK-T1-M0: ldr {{r[0-9]}}, [r1]
; CHECK-T1-M0: dmb
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: ___sync_val_compare_and_swap_4
; CHECK-T1: ___sync_val_compare_and_swap_4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0]
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r1]
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMETAL: add r0,
ret i32 %tmp
}
define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
; CHECK-LABEL: store_store_release
store atomic i32 %val1, i32* %mem1 release, align 4
store atomic i32 %val2, i32* %mem2 release, align 4
; CHECK: dmb
; CHECK: str r1, [r0]
; CHECK: dmb
; CHECK: str r3, [r2]
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: ___sync_lock_test_and_set
; CHECK-T1: ___sync_lock_test_and_set
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: dmb
; CHECK-T1-M0: str r1, [r0]
; CHECK-T1-M0: dmb
; CHECK-T1-M0: str r3, [r2]
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMTEAL: str r1, [r0]
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMTEAL: str r3, [r2]
ret void
}
define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
; CHECK-LABEL: load_fence_store_monotonic
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load atomic i32, i32* %mem1 monotonic, align 4
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
fence seq_cst
store atomic i32 %val, i32* %mem2 monotonic, align 4
; CHECK: ldr [[R0:r[0-9]]], [r0]
; CHECK: dmb
; CHECK: str [[R0]], [r1]
[Cortex-M0] Atomic lowering Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls. Reviewers: rengolin, efriedma, t.p.northover, jmolloy Subscribers: efriedma, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26120 llvm-svn: 285969
2016-11-04 05:49:08 +08:00
; CHECK-T1-M0: ldr [[R0:r[0-9]]], [r0]
; CHECK-T1-M0: dmb
; CHECK-T1-M0: str [[R0]], [r1]
ARM: stop emitting blx instructions for most calls on MachO. I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
2016-05-11 03:17:47 +08:00
; CHECK-T1: ldr [[R0:r[0-9]]], [{{r[0-9]+}}]
; CHECK-T1: {{dmb|bl ___sync_synchronize}}
; CHECK-T1: str [[R0]], [{{r[0-9]+}}]
Add a thread-model knob for lowering atomics on baremetal & single threaded systems http://reviews.llvm.org/D4984 llvm-svn: 216182
2014-08-21 22:35:47 +08:00
; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0]
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMETAL: str [[R0]], [r1]
ret void
}