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llvm-project/llvm/test/MC/AMDGPU/literal16-err.s

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AMDGPU: Fix handling of 16-bit immediates Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306
2016-12-10 08:39:12 +08:00
// XFAIL: *
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
v_add_f16 v1, 0xfffff, v2
// NOVI: 19: error: invalid operand for instruction
v_add_f16 v1, 0x10000, v2
// NOVI: 19: error: invalid operand for instruction
v_add_f16 v1, v2, -0.0
v_add_f16 v1, v2, 1
// FIXME: Should give truncate error
v_add_f16 v1, -32769, v2
v_add_f16 v1, 65536, v2
v_add_f32 v1, 4294967296, v2
v_add_f32 v1, 0x0000000100000000, v2
v_and_b32 v1, 0x0000000100000000, v2