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llvm-project/llvm/test/CodeGen/X86/shift-bmi2.ll

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Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; RUN: llc -mtriple=i386-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI2 %s
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI264 %s
define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
entry:
%shl = shl i32 %x, %shamt
; BMI2: shl32
; BMI2: shlxl
; BMI2: ret
; BMI264: shl32
; BMI264: shlxl
; BMI264: ret
ret i32 %shl
}
define i32 @shl32i(i32 %x) nounwind uwtable readnone {
entry:
%shl = shl i32 %x, 5
; BMI2: shl32i
; BMI2-NOT: shlxl
; BMI2: ret
; BMI264: shl32i
; BMI264-NOT: shlxl
; BMI264: ret
ret i32 %shl
}
define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, %shamt
; BMI2: shl32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; Source order scheduling prevents folding, rdar:14208996.
; BMI2: shlxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI2: ret
; BMI264: shl32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: shlxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i32 %shl
}
define i32 @shl32pi(i32* %p) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i32 %x, 5
; BMI2: shl32pi
; BMI2-NOT: shlxl
; BMI2: ret
; BMI264: shl32pi
; BMI264-NOT: shlxl
; BMI264: ret
ret i32 %shl
}
define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
entry:
%shl = shl i64 %x, %shamt
; BMI264: shl64
; BMI264: shlxq
; BMI264: ret
ret i64 %shl
}
define i64 @shl64i(i64 %x) nounwind uwtable readnone {
entry:
%shl = shl i64 %x, 7
; BMI264: shl64i
; BMI264-NOT: shlxq
; BMI264: ret
ret i64 %shl
}
define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, %shamt
; BMI264: shl64p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: shlxq %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i64 %shl
}
define i64 @shl64pi(i64* %p) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = shl i64 %x, 7
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
; BMI264: shl64pi
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264-NOT: shlxq
; BMI264: ret
ret i64 %shl
}
define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
entry:
%shl = lshr i32 %x, %shamt
; BMI2: lshr32
; BMI2: shrxl
; BMI2: ret
; BMI264: lshr32
; BMI264: shrxl
; BMI264: ret
ret i32 %shl
}
define i32 @lshr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i32 %x, %shamt
; BMI2: lshr32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; Source order scheduling prevents folding, rdar:14208996.
; BMI2: shrxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI2: ret
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
; BMI264: lshr32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: shrxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i32 %shl
}
define i64 @lshr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
entry:
%shl = lshr i64 %x, %shamt
; BMI264: lshr64
; BMI264: shrxq
; BMI264: ret
ret i64 %shl
}
define i64 @lshr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = lshr i64 %x, %shamt
; BMI264: lshr64p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: shrxq %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i64 %shl
}
define i32 @ashr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
entry:
%shl = ashr i32 %x, %shamt
; BMI2: ashr32
; BMI2: sarxl
; BMI2: ret
; BMI264: ashr32
; BMI264: sarxl
; BMI264: ret
ret i32 %shl
}
define i32 @ashr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i32, i32* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i32 %x, %shamt
; BMI2: ashr32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; Source order scheduling prevents folding, rdar:14208996.
; BMI2: sarxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI2: ret
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
; BMI264: ashr32p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: sarxl %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i32 %shl
}
define i64 @ashr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
entry:
%shl = ashr i64 %x, %shamt
; BMI264: ashr64
; BMI264: sarxq
; BMI264: ret
ret i64 %shl
}
define i64 @ashr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x = load i64, i64* %p
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
%shl = ashr i64 %x, %shamt
; BMI264: ashr64p
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; BMI264: sarxq %{{.+}}, %{{.+}}, %{{.+}}
Add SARX/SHRX/SHLX code generation support llvm-svn: 164675
2012-09-26 16:26:25 +08:00
; BMI264: ret
ret i64 %shl
}