2011-10-02 00:41:13 +08:00
|
|
|
//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
|
2005-04-22 08:00:37 +08:00
|
|
|
//
|
2003-10-21 04:20:30 +08:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
|
//
|
2007-12-30 04:37:13 +08:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-22 08:00:37 +08:00
|
|
|
//
|
2003-10-21 04:20:30 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2003-10-06 03:27:59 +08:00
|
|
|
//
|
2011-10-02 00:41:13 +08:00
|
|
|
// This file contains the main function for LLVM's TableGen.
|
2003-10-06 03:27:59 +08:00
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2012-06-11 23:37:55 +08:00
|
|
|
#include "TableGenBackends.h" // Declares all backends.
|
2009-07-09 02:44:05 +08:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2016-01-04 12:51:51 +08:00
|
|
|
#include "llvm/Support/ManagedStatic.h"
|
2009-07-09 02:44:05 +08:00
|
|
|
#include "llvm/Support/PrettyStackTrace.h"
|
2010-11-30 02:16:10 +08:00
|
|
|
#include "llvm/Support/Signals.h"
|
2011-10-02 00:41:13 +08:00
|
|
|
#include "llvm/TableGen/Main.h"
|
|
|
|
|
#include "llvm/TableGen/Record.h"
|
2014-06-17 21:10:38 +08:00
|
|
|
#include "llvm/TableGen/SetTheory.h"
|
2011-10-02 00:41:13 +08:00
|
|
|
|
2004-08-01 11:55:39 +08:00
|
|
|
using namespace llvm;
|
2003-11-12 06:41:34 +08:00
|
|
|
|
2003-10-06 03:27:59 +08:00
|
|
|
enum ActionType {
|
|
|
|
|
PrintRecords,
|
|
|
|
|
GenEmitter,
|
2011-06-28 02:32:37 +08:00
|
|
|
GenRegisterInfo,
|
2011-06-29 04:07:07 +08:00
|
|
|
GenInstrInfo,
|
2017-11-14 23:35:15 +08:00
|
|
|
GenInstrDocs,
|
2011-06-29 04:07:07 +08:00
|
|
|
GenAsmWriter,
|
|
|
|
|
GenAsmMatcher,
|
2009-11-25 10:13:23 +08:00
|
|
|
GenDisassembler,
|
2011-07-09 01:36:35 +08:00
|
|
|
GenPseudoLowering,
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
GenCompressInst,
|
2007-02-28 06:08:27 +08:00
|
|
|
GenCallingConv,
|
2005-09-03 09:14:03 +08:00
|
|
|
GenDAGISel,
|
2011-12-02 05:10:21 +08:00
|
|
|
GenDFAPacketizer,
|
2008-08-14 04:19:35 +08:00
|
|
|
GenFastISel,
|
2005-10-22 03:05:19 +08:00
|
|
|
GenSubtarget,
|
2018-06-23 10:02:38 +08:00
|
|
|
GenIntrinsicEnums,
|
|
|
|
|
GenIntrinsicImpl,
|
|
|
|
|
GenTgtIntrinsicEnums,
|
|
|
|
|
GenTgtIntrinsicImpl,
|
2011-06-04 12:11:37 +08:00
|
|
|
PrintEnums,
|
2012-12-05 08:29:32 +08:00
|
|
|
PrintSets,
|
2013-03-22 07:40:38 +08:00
|
|
|
GenOptParserDefs,
|
2015-11-12 04:35:42 +08:00
|
|
|
GenCTags,
|
2016-07-06 05:23:04 +08:00
|
|
|
GenAttributes,
|
|
|
|
|
GenSearchableTables,
|
2016-12-22 07:26:20 +08:00
|
|
|
GenGlobalISel,
|
2017-03-07 16:11:19 +08:00
|
|
|
GenX86EVEX2VEXTables,
|
2017-10-08 17:20:32 +08:00
|
|
|
GenX86FoldTables,
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
|
|
|
GenRegisterBank,
|
2003-10-06 03:27:59 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
|
cl::opt<ActionType>
|
|
|
|
|
Action(cl::desc("Action to perform:"),
|
|
|
|
|
cl::values(clEnumValN(PrintRecords, "print-records",
|
|
|
|
|
"Print all records to stdout (default)"),
|
|
|
|
|
clEnumValN(GenEmitter, "gen-emitter",
|
|
|
|
|
"Generate machine code emitter"),
|
2011-06-24 09:44:41 +08:00
|
|
|
clEnumValN(GenRegisterInfo, "gen-register-info",
|
2011-06-28 02:32:37 +08:00
|
|
|
"Generate registers and register classes info"),
|
2011-06-29 04:07:07 +08:00
|
|
|
clEnumValN(GenInstrInfo, "gen-instr-info",
|
2003-10-06 03:27:59 +08:00
|
|
|
"Generate instruction descriptions"),
|
2017-11-14 23:35:15 +08:00
|
|
|
clEnumValN(GenInstrDocs, "gen-instr-docs",
|
|
|
|
|
"Generate instruction documentation"),
|
2007-02-28 06:08:27 +08:00
|
|
|
clEnumValN(GenCallingConv, "gen-callingconv",
|
|
|
|
|
"Generate calling convention descriptions"),
|
2004-08-01 13:59:33 +08:00
|
|
|
clEnumValN(GenAsmWriter, "gen-asm-writer",
|
|
|
|
|
"Generate assembly writer"),
|
2009-11-25 10:13:23 +08:00
|
|
|
clEnumValN(GenDisassembler, "gen-disassembler",
|
|
|
|
|
"Generate disassembler"),
|
2011-07-09 01:36:35 +08:00
|
|
|
clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
|
|
|
|
|
"Generate pseudo instruction lowering"),
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
|
|
|
|
|
"Generate RISCV compressed instructions."),
|
2009-07-12 03:39:44 +08:00
|
|
|
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
|
|
|
|
|
"Generate assembly instruction matcher"),
|
2005-09-03 09:14:03 +08:00
|
|
|
clEnumValN(GenDAGISel, "gen-dag-isel",
|
|
|
|
|
"Generate a DAG instruction selector"),
|
2011-12-02 05:10:21 +08:00
|
|
|
clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
|
|
|
|
|
"Generate DFA Packetizer for VLIW targets"),
|
2008-08-14 04:19:35 +08:00
|
|
|
clEnumValN(GenFastISel, "gen-fast-isel",
|
|
|
|
|
"Generate a \"fast\" instruction selector"),
|
2005-10-22 03:05:19 +08:00
|
|
|
clEnumValN(GenSubtarget, "gen-subtarget",
|
|
|
|
|
"Generate subtarget enumerations"),
|
2018-06-23 10:02:38 +08:00
|
|
|
clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
|
|
|
|
|
"Generate intrinsic enums"),
|
|
|
|
|
clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
|
2006-03-03 10:32:46 +08:00
|
|
|
"Generate intrinsic information"),
|
2018-06-23 10:02:38 +08:00
|
|
|
clEnumValN(GenTgtIntrinsicEnums, "gen-tgt-intrinsic-enums",
|
|
|
|
|
"Generate target intrinsic enums"),
|
|
|
|
|
clEnumValN(GenTgtIntrinsicImpl, "gen-tgt-intrinsic-impl",
|
2009-02-05 09:49:45 +08:00
|
|
|
"Generate target intrinsic information"),
|
2003-10-06 03:27:59 +08:00
|
|
|
clEnumValN(PrintEnums, "print-enums",
|
|
|
|
|
"Print enum values for a class"),
|
2011-06-04 12:11:37 +08:00
|
|
|
clEnumValN(PrintSets, "print-sets",
|
|
|
|
|
"Print expanded sets for testing DAG exprs"),
|
2012-12-05 08:29:32 +08:00
|
|
|
clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
|
|
|
|
|
"Generate option definitions"),
|
2013-03-22 07:40:38 +08:00
|
|
|
clEnumValN(GenCTags, "gen-ctags",
|
|
|
|
|
"Generate ctags-compatible index"),
|
2015-11-12 04:35:42 +08:00
|
|
|
clEnumValN(GenAttributes, "gen-attrs",
|
|
|
|
|
"Generate attributes"),
|
2016-07-06 05:23:04 +08:00
|
|
|
clEnumValN(GenSearchableTables, "gen-searchable-tables",
|
2016-12-22 07:26:20 +08:00
|
|
|
"Generate generic binary-searchable table"),
|
|
|
|
|
clEnumValN(GenGlobalISel, "gen-global-isel",
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
|
|
|
"Generate GlobalISel selector"),
|
2017-03-07 16:11:19 +08:00
|
|
|
clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
|
|
|
|
|
"Generate X86 EVEX to VEX compress tables"),
|
2017-10-08 17:20:32 +08:00
|
|
|
clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
|
|
|
|
|
"Generate X86 fold tables"),
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
|
|
|
clEnumValN(GenRegisterBank, "gen-register-bank",
|
|
|
|
|
"Generate registers bank descriptions")));
|
2003-10-06 03:27:59 +08:00
|
|
|
|
2017-03-27 21:15:13 +08:00
|
|
|
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
|
2003-10-06 03:27:59 +08:00
|
|
|
cl::opt<std::string>
|
|
|
|
|
Class("class", cl::desc("Print Enum list for this class"),
|
2017-03-27 21:15:13 +08:00
|
|
|
cl::value_desc("class name"), cl::cat(PrintEnumsCat));
|
2012-06-11 23:37:55 +08:00
|
|
|
|
2012-10-04 05:29:19 +08:00
|
|
|
bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
|
|
|
|
|
switch (Action) {
|
|
|
|
|
case PrintRecords:
|
|
|
|
|
OS << Records; // No argument, dump all contents
|
|
|
|
|
break;
|
|
|
|
|
case GenEmitter:
|
|
|
|
|
EmitCodeEmitter(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenRegisterInfo:
|
|
|
|
|
EmitRegisterInfo(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenInstrInfo:
|
|
|
|
|
EmitInstrInfo(Records, OS);
|
|
|
|
|
break;
|
2017-11-14 23:35:15 +08:00
|
|
|
case GenInstrDocs:
|
|
|
|
|
EmitInstrDocs(Records, OS);
|
|
|
|
|
break;
|
2012-10-04 05:29:19 +08:00
|
|
|
case GenCallingConv:
|
|
|
|
|
EmitCallingConv(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenAsmWriter:
|
|
|
|
|
EmitAsmWriter(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenAsmMatcher:
|
|
|
|
|
EmitAsmMatcher(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenDisassembler:
|
|
|
|
|
EmitDisassembler(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenPseudoLowering:
|
|
|
|
|
EmitPseudoLowering(Records, OS);
|
|
|
|
|
break;
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
case GenCompressInst:
|
|
|
|
|
EmitCompressInst(Records, OS);
|
|
|
|
|
break;
|
2012-10-04 05:29:19 +08:00
|
|
|
case GenDAGISel:
|
|
|
|
|
EmitDAGISel(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenDFAPacketizer:
|
|
|
|
|
EmitDFAPacketizer(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenFastISel:
|
|
|
|
|
EmitFastISel(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenSubtarget:
|
|
|
|
|
EmitSubtarget(Records, OS);
|
|
|
|
|
break;
|
2018-06-23 10:02:38 +08:00
|
|
|
case GenIntrinsicEnums:
|
|
|
|
|
EmitIntrinsicEnums(Records, OS);
|
2012-10-04 05:29:19 +08:00
|
|
|
break;
|
2018-06-23 10:02:38 +08:00
|
|
|
case GenIntrinsicImpl:
|
|
|
|
|
EmitIntrinsicImpl(Records, OS);
|
|
|
|
|
break;
|
|
|
|
|
case GenTgtIntrinsicEnums:
|
|
|
|
|
EmitIntrinsicEnums(Records, OS, true);
|
|
|
|
|
break;
|
|
|
|
|
case GenTgtIntrinsicImpl:
|
|
|
|
|
EmitIntrinsicImpl(Records, OS, true);
|
2012-10-04 05:29:19 +08:00
|
|
|
break;
|
2012-12-05 08:29:32 +08:00
|
|
|
case GenOptParserDefs:
|
|
|
|
|
EmitOptParser(Records, OS);
|
|
|
|
|
break;
|
2012-10-04 05:29:19 +08:00
|
|
|
case PrintEnums:
|
|
|
|
|
{
|
2014-12-11 15:04:54 +08:00
|
|
|
for (Record *Rec : Records.getAllDerivedDefinitions(Class))
|
|
|
|
|
OS << Rec->getName() << ", ";
|
2012-10-04 05:29:19 +08:00
|
|
|
OS << "\n";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case PrintSets:
|
|
|
|
|
{
|
|
|
|
|
SetTheory Sets;
|
|
|
|
|
Sets.addFieldExpander("Set", "Elements");
|
2014-12-11 15:04:54 +08:00
|
|
|
for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
|
|
|
|
|
OS << Rec->getName() << " = [";
|
|
|
|
|
const std::vector<Record*> *Elts = Sets.expand(Rec);
|
2012-10-04 05:29:19 +08:00
|
|
|
assert(Elts && "Couldn't expand Set instance");
|
2014-12-11 15:04:54 +08:00
|
|
|
for (Record *Elt : *Elts)
|
|
|
|
|
OS << ' ' << Elt->getName();
|
2012-10-04 05:29:19 +08:00
|
|
|
OS << " ]\n";
|
2003-11-12 06:41:34 +08:00
|
|
|
}
|
2012-10-04 05:29:19 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2013-03-22 07:40:38 +08:00
|
|
|
case GenCTags:
|
|
|
|
|
EmitCTags(Records, OS);
|
|
|
|
|
break;
|
2015-11-12 04:35:42 +08:00
|
|
|
case GenAttributes:
|
|
|
|
|
EmitAttributes(Records, OS);
|
|
|
|
|
break;
|
2016-07-06 05:23:04 +08:00
|
|
|
case GenSearchableTables:
|
|
|
|
|
EmitSearchableTables(Records, OS);
|
|
|
|
|
break;
|
2016-12-22 07:26:20 +08:00
|
|
|
case GenGlobalISel:
|
|
|
|
|
EmitGlobalISel(Records, OS);
|
2017-02-03 22:18:35 +08:00
|
|
|
break;
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
|
|
|
case GenRegisterBank:
|
|
|
|
|
EmitRegisterBank(Records, OS);
|
2016-12-22 07:26:20 +08:00
|
|
|
break;
|
2017-03-07 16:11:19 +08:00
|
|
|
case GenX86EVEX2VEXTables:
|
|
|
|
|
EmitX86EVEX2VEXTables(Records, OS);
|
|
|
|
|
break;
|
2017-10-08 17:20:32 +08:00
|
|
|
case GenX86FoldTables:
|
|
|
|
|
EmitX86FoldTables(Records, OS);
|
|
|
|
|
break;
|
2012-10-04 05:29:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2011-12-20 10:50:00 +08:00
|
|
|
}
|
2011-10-02 00:41:13 +08:00
|
|
|
|
|
|
|
|
int main(int argc, char **argv) {
|
2016-06-09 08:53:21 +08:00
|
|
|
sys::PrintStackTraceOnErrorSignal(argv[0]);
|
2011-10-02 00:41:13 +08:00
|
|
|
PrettyStackTraceProgram X(argc, argv);
|
|
|
|
|
cl::ParseCommandLineOptions(argc, argv);
|
2010-05-05 12:13:08 +08:00
|
|
|
|
2016-01-04 12:51:51 +08:00
|
|
|
llvm_shutdown_obj Y;
|
|
|
|
|
|
2012-10-04 05:29:19 +08:00
|
|
|
return TableGenMain(argv[0], &LLVMTableGenMain);
|
2003-10-06 03:27:59 +08:00
|
|
|
}
|
2014-01-10 16:05:42 +08:00
|
|
|
|
2014-01-15 15:59:37 +08:00
|
|
|
#ifdef __has_feature
|
|
|
|
|
#if __has_feature(address_sanitizer)
|
|
|
|
|
#include <sanitizer/lsan_interface.h>
|
2014-01-10 16:05:42 +08:00
|
|
|
// Disable LeakSanitizer for this binary as it has too many leaks that are not
|
2014-01-15 15:59:37 +08:00
|
|
|
// very interesting to fix. See compiler-rt/include/sanitizer/lsan_interface.h .
|
2017-09-11 21:50:39 +08:00
|
|
|
LLVM_ATTRIBUTE_USED int __lsan_is_turned_off() { return 1; }
|
2014-01-15 15:59:37 +08:00
|
|
|
#endif // __has_feature(address_sanitizer)
|
|
|
|
|
#endif // defined(__has_feature)
|