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llvm-project/llvm/lib/Target/ARM/ARMScheduleA9.td

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Split A8/A9 itins - they already were too big. llvm-svn: 100672
2010-04-08 02:22:11 +08:00
//=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. llvm-svn: 106988
2010-06-28 12:27:01 +08:00
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. llvm-svn: 106988
2010-06-28 12:27:01 +08:00
//
Add fake v7 itineraries for now. llvm-svn: 76612
2009-07-22 02:54:14 +08:00
//===----------------------------------------------------------------------===//
//
Split A8/A9 itins - they already were too big. llvm-svn: 100672
2010-04-08 02:22:11 +08:00
// This file defines the itinerary class data for the ARM Cortex A9 processors.
Add fake v7 itineraries for now. llvm-svn: 76612
2009-07-22 02:54:14 +08:00
//
//===----------------------------------------------------------------------===//
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
// ===---------------------------------------------------------------------===//
// This section contains legacy support for itineraries. This is
// required until SD and PostRA schedulers are replaced by MachineScheduler.
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
// Reference Manual".
//
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
// Functional units
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
def A9_Issue0 : FuncUnit; // Issue 0
def A9_Issue1 : FuncUnit; // Issue 1
def A9_Branch : FuncUnit; // Branch
def A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0
def A9_ALU1 : FuncUnit; // ALU pipeline 1
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
def A9_AGU : FuncUnit; // Address generation unit for ld / st
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
def A9_NPipe : FuncUnit; // NEON pipeline
def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
def A9_LSUnit : FuncUnit; // L/S Unit
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
def A9_DRegsN : FuncUnit; // FP register set, NEON side
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
// Bypasses
def A9_LdBypass : Bypass;
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
def CortexA9Itineraries : ProcessorItineraries<
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
[A9_LdBypass], [
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Two fully-pipelined integer ALU pipelines
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 08:49:25 +08:00
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
// Move instructions, unconditional
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Sorry, several patches in one. TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
2011-01-20 16:34:58 +08:00
InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [3]>,
InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_AGU], 0>,
InstrStage<1, [A9_LSUnit]>], [5]>,
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 08:49:25 +08:00
//
// MVN instructions
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
[1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
[1, 1], [NoBypass, A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[2, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 1, 1]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
// No operand cycles
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
// Binary Instructions that produce a result
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[1, 1], [NoBypass, A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 1, 1, 1],
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
[NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 08:27:46 +08:00
// Bitwise Instructions that produce a result
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 08:27:46 +08:00
//
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Unary Instructions that produce a result
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
// CLZ, RBIT, etc.
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
// BFC, BFI, UBFX, SBFX
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 08:49:35 +08:00
// Zero and sign extension instructions
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 08:49:35 +08:00
//
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Compare instructions
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
[1], [A9_LdBypass]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>],
[1, 1], [A9_LdBypass, A9_LdBypass]>,
Fix the ARM IIC_iCMPsi itinerary and add an important assert. llvm-svn: 122794
2011-01-04 08:32:57 +08:00
InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>],
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[1, 1], [A9_LdBypass, NoBypass]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
//
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 08:49:25 +08:00
// Test instructions
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 08:49:25 +08:00
//
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Move instructions, conditional
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
// FIXME: Correctly model the extra input dep on the destination.
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
Conditional moves are slightly more expensive than moves. llvm-svn: 118985
2010-11-13 13:14:20 +08:00
InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>,
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Integer multiply pipeline
//
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0]>],
[3, 1, 1, 1]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<2, [A9_ALU0]>],
[4, 1, 1, 1]>,
InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<3, [A9_ALU0]>],
[4, 5, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
// Integer load pipeline
// FIXME: The timings are some rough approximations
//
// Immediate offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 1], [A9_LdBypass]>,
// FIXME: If address is 64-bit aligned, AGU cycles is 1.
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 3, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Register offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 3, 1, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Scaled register offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
InstrStage<1, [A9_LSUnit], 0>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[5, 1, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Immediate offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 2, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 3, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Register offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 2, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 3, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[3, 3, 1, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Scaled register offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
[4, 3, 1, 1], [A9_LdBypass]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<2, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[5, 4, 1, 1], [A9_LdBypass]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
// Load multiple, def is the 5th operand.
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// FIXME: This assumes 3 to 4 registers.
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<2, [A9_LSUnit]>],
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
[1, 1, 1, 1, 3],
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
-1>, // dynamic uops
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
//
// Load multiple + update, defs are the 1st and 5th operands.
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<2, [A9_LSUnit]>],
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
[2, 1, 1, 1, 3],
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
-1>, // dynamic uops
Fix LDM_RET schedule itinery. llvm-svn: 113435
2010-09-09 06:57:08 +08:00
//
// Load multiple plus branch
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_AGU], 1>,
InstrStage<2, [A9_LSUnit]>,
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrStage<1, [A9_Branch]>],
[1, 2, 1, 1, 3],
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
-1>, // dynamic uops
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
//
// Pop, def is the 3rd operand.
InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<2, [A9_LSUnit]>],
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
[1, 1, 3],
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
[NoBypass, NoBypass, A9_LdBypass],
-1>, // dynamic uops
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
//
// Pop + branch, def is the 3rd operand.
InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<2, [A9_LSUnit]>,
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrStage<1, [A9_Branch]>],
[1, 1, 3],
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
[NoBypass, NoBypass, A9_LdBypass],
-1>, // dynamic uops
More pseudo instruction scheduling itinerary fixes. llvm-svn: 114768
2010-09-25 06:41:41 +08:00
//
// iLoadi + iALUr for t2LDRpci_pic.
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrStage<1, [A9_ALU0, A9_ALU1]>],
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP pipeline forwarding path. llvm-svn: 115098
2010-09-30 06:42:35 +08:00
[2, 1]>,
More pseudo instruction scheduling itinerary fixes. llvm-svn: 114768
2010-09-25 06:41:41 +08:00
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
// Integer store pipeline
///
// Immediate offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [1, 1]>,
ARM instruction itinerary fixes: 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
2010-09-30 09:08:25 +08:00
// FIXME: If address is 64-bit aligned, AGU cycles is 1.
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Register offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Scaled register offset
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Immediate offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Register offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[2, 1, 1, 1]>,
InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>],
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[3, 1, 1, 1]>,
InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Scaled register offset with update
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[2, 1, 1, 1]>,
InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<2, [A9_AGU], 1>,
InstrStage<1, [A9_LSUnit]>],
Major changes to Cortex-A9 itinerary. 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
2010-10-03 10:03:59 +08:00
[3, 1, 1, 1]>,
Some rough approximations for load/stores on A9 llvm-svn: 105108
2010-05-30 03:25:34 +08:00
//
// Store multiple
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[], [], -1>, // dynamic uops
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
//
// Store multiple + update
InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_AGU], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[2], [], -1>, // dynamic uops
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
2010-11-03 14:34:55 +08:00
//
// Preload
InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
// Branch
//
// no delay slots, so the latency of a branch is unimportant
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
2010-10-06 14:27:31 +08:00
InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>,
InstrStage<1, [A9_Issue1], 0>,
InstrStage<1, [A9_Branch]>]>,
Add some integer instruction itineraries for A9 llvm-svn: 105106
2010-05-30 03:25:17 +08:00
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. llvm-svn: 100646
2010-04-08 02:19:40 +08:00
// VFP and NEON shares the same register file. This means that every VFP
// instruction should wait for full completion of the consecutive NEON
// instruction and vice-versa. We model this behavior with two artificial FUs:
// DRegsVFP and DRegsVFP.
//
// Every VFP instruction:
// - Acquires DRegsVFP resource for 1 cycle
Proper cycle times for locks, since wbck latency can be larger than fwd latency. llvm-svn: 100648
2010-04-08 02:19:51 +08:00
// - Reserves DRegsN resource for the whole duration (including time to
// register file writeback!).
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. llvm-svn: 100646
2010-04-08 02:19:40 +08:00
// Every NEON instruction does the same but with FUs swapped.
//
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. llvm-svn: 106988
2010-06-28 12:27:01 +08:00
// Since the reserved FU cannot be acquired, this models precisely
// "cross-domain" stalls.
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
// VFP
// Issue through integer pipeline, and execute in NEON unit.
// FP Special Register to Integer Register File Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Fix fpscr <-> GPR latency info. llvm-svn: 117737
2010-10-30 07:16:55 +08:00
InstrStage<1, [A9_NPipe]>],
[1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 2 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<3, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 2 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<3, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP Compare
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 4 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP Compare
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 4 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single to Double FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double to Single FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. llvm-svn: 100647
2010-04-08 02:19:46 +08:00
//
// Single to Half FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. llvm-svn: 100647
2010-04-08 02:19:46 +08:00
//
// Half to Single FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<3, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 1]>,
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. llvm-svn: 100647
2010-04-08 02:19:46 +08:00
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-Precision FP to Integer Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-Precision FP to Integer Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Integer to Single-Precision FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Integer to Double-Precision FP Convert
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP ALU
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP ALU
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<5, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP Multiply
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<6, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[5, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP Multiply
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<7, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP MAC
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<9, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. llvm-svn: 117531
2010-10-28 14:47:08 +08:00
[8, 1, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP MAC
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<10, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. llvm-svn: 117531
2010-10-28 14:47:08 +08:00
[9, 1, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
Fix a number of problems with ARM fused multiply add/subtract instructions. 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
2012-04-11 08:13:00 +08:00
// Single-precision Fused FP MAC
InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<9, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[8, 1, 1, 1]>,
//
// Double-precision Fused FP MAC
InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<10, [A9_DRegsN], 0, Reserved>,
InstrStage<2, [A9_NPipe]>],
[9, 1, 1, 1]>,
//
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
// Single-precision FP DIV
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<16, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<10, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[15, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP DIV
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<26, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<20, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[25, 1, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Single-precision FP SQRT
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<18, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<13, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[17, 1]>,
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
//
// Double-precision FP SQRT
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<33, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<28, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[32, 1]>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
//
// Integer to Single-precision Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
// Extra 1 latency cycle since wbck is 2 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<3, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1]>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
//
// Integer to Double-precision Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsVFP], 0, Required>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
// Extra 1 latency cycle since wbck is 2 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<3, [A9_DRegsN], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[1, 1, 1]>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
//
// Single-precision to Integer Move
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
//
// On A9 move-from-VFP is free to issue with no stall if other VFP
// operations are in flight. I assume it still can't dual-issue though.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
InstrStage<1, [A9_MUX0], 0>],
putback r116983 and fix simple-fp-encoding.ll tests llvm-svn: 116992
2010-10-21 11:40:16 +08:00
[2, 1]>,
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( llvm-svn: 100650
2010-04-08 02:20:02 +08:00
//
// Double-precision to Integer Move
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
//
// On A9 move-from-VFP is free to issue with no stall if other VFP
// operations are in flight. I assume it still can't dual-issue though.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
InstrStage<1, [A9_MUX0], 0>],
putback r116983 and fix simple-fp-encoding.ll tests llvm-svn: 116992
2010-10-21 11:40:16 +08:00
[2, 1, 1]>,
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// Single-precision FP Load
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Add operand cycles for vldr / vstr. llvm-svn: 115353
2010-10-02 05:40:30 +08:00
[1, 1]>,
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// Double-precision FP Load
Add operand cycles for vldr / vstr. llvm-svn: 115353
2010-10-02 05:40:30 +08:00
// FIXME: Result latency is 1 if address is 64-bit aligned.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Add operand cycles for vldr / vstr. llvm-svn: 115353
2010-10-02 05:40:30 +08:00
[2, 1]>,
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// FP Load Multiple
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
// FIXME: assumes 2 doubles which requires 2 LS cycles.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[1, 1, 1, 1], [], -1>, // dynamic uops
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 09:50:48 +08:00
//
// FP Load Multiple + update
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
// FIXME: assumes 2 doubles which requires 2 LS cycles.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 09:50:48 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[2, 1, 1, 1], [], -1>, // dynamic uops
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// Single-precision FP Store
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Add operand cycles for vldr / vstr. llvm-svn: 115353
2010-10-02 05:40:30 +08:00
[1, 1]>,
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// Double-precision FP Store
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<1, [A9_LSUnit]>],
Add operand cycles for vldr / vstr. llvm-svn: 115353
2010-10-02 05:40:30 +08:00
[1, 1]>,
Add some crude itin approximation for VFP load / stores on A9 llvm-svn: 100671
2010-04-08 02:22:03 +08:00
//
// FP Store Multiple
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
// FIXME: assumes 2 doubles which requires 2 LS cycles.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[1, 1, 1, 1], [], -1>, // dynamic uops
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 09:50:48 +08:00
//
// FP Store Multiple + update
Improvements for the Cortex-A9 scheduling itineraries. llvm-svn: 129770
2011-04-20 02:11:36 +08:00
// FIXME: assumes 2 doubles which requires 2 LS cycles.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. llvm-svn: 115898
2010-10-07 09:50:48 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<1, [A9_NPipe], 0>,
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
2012-07-03 02:10:42 +08:00
InstrStage<2, [A9_LSUnit]>],
[2, 1, 1, 1], [], -1>, // dynamic uops
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
// NEON
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
// VLD1
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[1, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x2
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[1, 1, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x3
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[1, 1, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x4
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[1, 1, 2, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[1, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x2u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[1, 1, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x3u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[1, 1, 2, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// VLD1x4u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[1, 1, 2, 2, 2, 1]>,
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
//
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 117964
2010-11-02 06:04:05 +08:00
// VLD1ln
InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[3, 1, 1, 1]>,
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 117964
2010-11-02 06:04:05 +08:00
//
// VLD1lnu
InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[3, 2, 1, 1, 1, 1]>,
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 117964
2010-11-02 06:04:05 +08:00
//
Add NEON VLD1-dup instructions (load 1 element to all lanes). llvm-svn: 120194
2010-11-27 14:35:16 +08:00
// VLD1dup
InstrItinData<IIC_VLD1dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 1]>,
Add NEON VLD1-dup instructions (load 1 element to all lanes). llvm-svn: 120194
2010-11-27 14:35:16 +08:00
//
// VLD1dupu
InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 2, 1, 1]>,
Add NEON VLD1-dup instructions (load 1 element to all lanes). llvm-svn: 120194
2010-11-27 14:35:16 +08:00
//
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
// VLD2
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// Extra latency cycles since wbck is 7 cycles
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
//
// VLD2x2
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[2, 3, 2, 3, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
//
// VLD2ln
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[3, 3, 1, 1, 1, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
//
// VLD2u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
// Extra latency cycles since wbck is 7 cycles
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 2, 2, 1, 1, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
//
// VLD2x2u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[2, 3, 2, 3, 2, 1]>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
//
// VLD2lnu
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134
2010-10-09 09:03:04 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[3, 3, 2, 1, 1, 1, 1, 1]>,
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
//
Add support for NEON VLD2-dup instructions. llvm-svn: 120236
2010-11-28 14:51:26 +08:00
// VLD2dup
InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 2, 1]>,
Add support for NEON VLD2-dup instructions. llvm-svn: 120236
2010-11-28 14:51:26 +08:00
//
// VLD2dupu
InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
[2, 2, 2, 1, 1]>,
Add support for NEON VLD2-dup instructions. llvm-svn: 120236
2010-11-28 14:51:26 +08:00
//
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
// VLD3
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 1]>,
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
//
// VLD3ln
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<5, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<5, [A9_LSUnit]>],
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
[5, 5, 6, 1, 1, 1, 1, 2]>,
//
// VLD3u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 2, 1]>,
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
//
// VLD3lnu
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<5, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<5, [A9_LSUnit]>],
Finish vld3 and vld4. llvm-svn: 116140
2010-10-09 09:45:34 +08:00
[5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
//
Add support for NEON VLD3-dup instructions. llvm-svn: 120312
2010-11-30 03:35:29 +08:00
// VLD3dup
InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 1]>,
//
// VLD3dupu
InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 2, 1, 1]>,
//
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
// VLD4
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 4, 1]>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
//
// VLD4ln
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
InstrStage<4, [A9_NPipe], 0>,
InstrStage<4, [A9_LSUnit]>],
[4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
//
// VLD4u
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
InstrStage<3, [A9_NPipe], 0>,
InstrStage<3, [A9_LSUnit]>],
[3, 3, 4, 4, 2, 1]>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
//
// VLD4lnu
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Add VLD4 scheduling itineraries. llvm-svn: 116143
2010-10-09 12:07:58 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
InstrStage<4, [A9_NPipe], 0>,
InstrStage<4, [A9_LSUnit]>],
[4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
Add some crude approximation for neon load/store instructions llvm-svn: 100670
2010-04-08 02:21:58 +08:00
//
Add support for NEON VLD3-dup instructions. The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
2010-11-30 08:00:35 +08:00
// VLD4dup
InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[2, 2, 3, 3, 1]>,
Add support for NEON VLD3-dup instructions. The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
2010-11-30 08:00:35 +08:00
//
// VLD4dupu
InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
[2, 2, 3, 3, 2, 1, 1]>,
Add support for NEON VLD3-dup instructions. The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
2010-11-30 08:00:35 +08:00
//
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
// VST1
InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1]>,
//
// VST1x2
InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1]>,
//
// VST1x3
InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2]>,
//
// VST1x4
InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2, 2]>,
//
// VST1u
InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1]>,
//
// VST1x2u
InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1]>,
//
// VST1x3u
InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2]>,
//
// VST1x4u
InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2, 2]>,
//
Add NEON VST1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 118069
2010-11-03 05:18:25 +08:00
// VST1ln
InstrItinData<IIC_VST1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Add NEON VST1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 118069
2010-11-03 05:18:25 +08:00
[1, 1, 1]>,
//
// VST1lnu
InstrItinData<IIC_VST1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Add NEON VST1-lane instructions. Partial fix for Radar 8599955. llvm-svn: 118069
2010-11-03 05:18:25 +08:00
[2, 1, 1, 1, 1]>,
//
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
// VST2
InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1]>,
//
// VST2x2
InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<3, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<3, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2, 2]>,
//
// VST2u
InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1]>,
//
// VST2x2u
InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<3, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<3, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2, 2]>,
//
// VST2ln
InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1]>,
//
// VST2lnu
InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe], 0>,
InstrStage<1, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1]>,
//
// VST3
InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2]>,
//
// VST3u
InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2]>,
//
// VST3ln
InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<3, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<3, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2]>,
//
// VST3lnu
InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. llvm-svn: 118134
2010-11-03 08:40:22 +08:00
InstrStage<3, [A9_NPipe], 0>,
Limit load / store issues (at least until we have a true multi-issue aware scheduler). llvm-svn: 116389
2010-10-13 09:54:21 +08:00
InstrStage<3, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2]>,
//
// VST4
InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2, 2]>,
//
// VST4u
InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2, 2]>,
//
// VST4ln
InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[1, 1, 1, 1, 2, 2]>,
//
// VST4lnu
InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
2011-04-19 09:21:49 +08:00
InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe], 0>,
InstrStage<2, [A9_LSUnit]>],
Proper VST scheduling itineraries. llvm-svn: 116251
2010-10-12 06:03:18 +08:00
[2, 1, 1, 1, 1, 1, 2, 2]>,
More A9 itineraries llvm-svn: 100655
2010-04-08 02:20:29 +08:00
//
// Double-register Integer Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2]>,
More A9 itineraries llvm-svn: 100655
2010-04-08 02:20:29 +08:00
//
// Quad-register Integer Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2]>,
More A9 itineraries llvm-svn: 100655
2010-04-08 02:20:29 +08:00
//
// Double-register Integer Q-Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
More A9 itineraries llvm-svn: 100655
2010-04-08 02:20:29 +08:00
//
// Quad-register Integer CountQ-Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Double-register Integer Binary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 2]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Quad-register Integer Binary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 2]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Double-register Integer Subtract
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 1]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Quad-register Integer Subtract
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 1]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Double-register Integer Shift
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 1]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
More shift itins for A9 llvm-svn: 100663
2010-04-08 02:21:16 +08:00
// Quad-register Integer Shift
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 1]>,
More shift itins for A9 llvm-svn: 100663
2010-04-08 02:21:16 +08:00
//
// Double-register Integer Shift (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 1]>,
More shift itins for A9 llvm-svn: 100663
2010-04-08 02:21:16 +08:00
//
// Quad-register Integer Shift (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 1]>,
More shift itins for A9 llvm-svn: 100663
2010-04-08 02:21:16 +08:00
//
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
// Double-register Integer Binary (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 2]>,
Some easy NEON scheduling goodness for A9 llvm-svn: 100651
2010-04-08 02:20:07 +08:00
//
// Quad-register Integer Binary (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 2]>,
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. llvm-svn: 100652
2010-04-08 02:20:13 +08:00
//
// Double-register Integer Subtract (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 1]>,
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. llvm-svn: 100652
2010-04-08 02:20:13 +08:00
//
// Quad-register Integer Subtract (4 cycle)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 1]>,
Fix itins for VABA llvm-svn: 100657
2010-04-08 02:20:42 +08:00
//
// Double-register Integer Count
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 2]>,
Fix itins for VABA llvm-svn: 100657
2010-04-08 02:20:42 +08:00
//
// Quad-register Integer Count
// Result written in N3, but that is relative to the last cycle of multicycle,
// so we use 4 for those cases
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 2]>,
Fix itins for VABA llvm-svn: 100657
2010-04-08 02:20:42 +08:00
//
// Double-register Absolute Difference and Accumulate
Fix an obvious cut-n-paste error. llvm-svn: 121307
2010-12-09 07:01:18 +08:00
InstrItinData<IIC_VABAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
Fix an obvious cut-n-paste error. llvm-svn: 121307
2010-12-09 07:01:18 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 2, 1]>,
Fix itins for VABA llvm-svn: 100657
2010-04-08 02:20:42 +08:00
//
// Quad-register Absolute Difference and Accumulate
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 2, 1]>,
Fix itins for VPAL llvm-svn: 100658
2010-04-08 02:20:47 +08:00
//
// Double-register Integer Pair Add Long
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 1]>,
Fix itins for VPAL llvm-svn: 100658
2010-04-08 02:20:47 +08:00
//
// Quad-register Integer Pair Add Long
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 1]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Double-register Integer Multiply (.8, .16)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 2, 2]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Quad-register Integer Multiply (.8, .16)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[7, 2, 2]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Double-register Integer Multiply (.32)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[7, 2, 1]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Quad-register Integer Multiply (.32)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 9 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<4, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[9, 2, 1]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Double-register Integer Multiply-Accumulate (.8, .16)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 2, 2]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Double-register Integer Multiply-Accumulate (.32)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[7, 3, 2, 1]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Quad-register Integer Multiply-Accumulate (.8, .16)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[7, 3, 2, 2]>,
Add MAC stuff for A9 llvm-svn: 100660
2010-04-08 02:20:58 +08:00
//
// Quad-register Integer Multiply-Accumulate (.32)
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 9 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<4, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[9, 3, 2, 1]>,
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
//
// Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
[1,1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Move Immediate
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3]>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
//
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
// Double-register Permute Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Quad-register Permute Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
[2, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Integer to Single-precision Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
putback r116983 and fix simple-fp-encoding.ll tests llvm-svn: 116992
2010-10-21 11:40:16 +08:00
[1, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Integer to Double-precision Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
putback r116983 and fix simple-fp-encoding.ll tests llvm-svn: 116992
2010-10-21 11:40:16 +08:00
[1, 1, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Single-precision to Integer Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Double-precision to Integer Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 2, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
// Integer to Lane Move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 1]>,
Add some A8-based approximation for instructions with unknown cycle times llvm-svn: 100669
2010-04-08 02:21:52 +08:00
//
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
// Vector narrow move
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
NEON scheduling info fix. vmov reg, reg are single cycle instructions. llvm-svn: 115344
2010-10-02 04:50:58 +08:00
[3, 1]>,
//
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
// Double-register FP Unary
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[5, 2]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
// Quad-register FP Unary
// Result written in N5, but that is relative to the last cycle of multicycle,
// so we use 6 for those cases
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 2]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
// Double-register FP Binary
// FIXME: We're using this itin for many instructions and [2, 2] here is too
// optimistic.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[5, 2, 2]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
//
// VPADD, etc.
InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[5, 1, 1]>,
//
// Double-register FP VMUL
InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[5, 2, 1]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
// Quad-register FP Binary
// Result written in N5, but that is relative to the last cycle of multicycle,
// so we use 6 for those cases
// FIXME: We're using this itin for many instructions and [2, 2] here is too
// optimistic.
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 7 cycles
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 2, 2]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
// Quad-register FP VMUL
InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_NPipe]>],
[6, 2, 1]>,
//
// Double-register FP Multiple-Accumulate
InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 7 cycles
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[6, 3, 2, 1]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
// Quad-register FP Multiple-Accumulate
// Result written in N9, but that is relative to the last cycle of multicycle,
// so we use 10 for those cases
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 9 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<4, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[8, 4, 2, 1]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
Fix a number of problems with ARM fused multiply add/subtract instructions. 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
2012-04-11 08:13:00 +08:00
// Double-register Fused FP Multiple-Accumulate
InstrItinData<IIC_VFMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 7 cycles
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe]>],
[6, 3, 2, 1]>,
//
// Quad-register Fused FP Multiple-Accumulate
// Result written in N9, but that is relative to the last cycle of multicycle,
// so we use 10 for those cases
InstrItinData<IIC_VFMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 9 cycles
InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
InstrStage<4, [A9_NPipe]>],
[8, 4, 2, 1]>,
//
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
// Double-register Reciprical Step
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 10 cycles
InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[9, 2, 2]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
// Quad-register Reciprical Step
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 11 cycles
InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
InstrStage<2, [A9_NPipe]>],
[10, 2, 2]>,
A9 NEON FP itins llvm-svn: 100665
2010-04-08 02:21:27 +08:00
//
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
// Double-register Permute
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 6 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 2, 1, 1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// Quad-register Permute
// Result written in N2, but that is relative to the last cycle of multicycle,
// so we use 3 for those cases
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 3, 1, 1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// Quad-register Permute (3 cycle issue)
// Result written in N2, but that is relative to the last cycle of multicycle,
// so we use 4 for those cases
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 8 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<3, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 4, 1, 1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// Double-register VEXT
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 6 cycles
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[2, 1, 1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// Quad-register VEXT
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<1, [A9_MUX0], 0>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrStage<1, [A9_DRegsN], 0, Required>,
// Extra latency cycles since wbck is 7 cycles
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
[3, 1, 2]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// VTB
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<2, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 2, 2, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<2, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 8 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<3, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 2, 3, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 8 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<3, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 2, 2, 3, 3, 1]>,
Some permute goodness for A9 llvm-svn: 100664
2010-04-08 02:21:22 +08:00
//
// VTBX
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 2, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 7 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[3, 1, 2, 2, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 8 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<3, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 2, 2, 3, 1]>,
More ARM scheduling itinerary fixes. llvm-svn: 116266
2010-10-12 07:41:41 +08:00
InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
InstrStage<1, [A9_DRegsN], 0, Required>,
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. llvm-svn: 100667
2010-04-08 02:21:41 +08:00
// Extra latency cycles since wbck is 8 cycles
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Fix r115332: correctly model AGU / NEON mux. llvm-svn: 115365
2010-10-02 06:52:29 +08:00
InstrStage<2, [A9_NPipe]>],
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. llvm-svn: 115332
2010-10-02 03:41:46 +08:00
[4, 1, 2, 2, 3, 3, 1]>
Some bits of A9 scheduling: VFP llvm-svn: 100643
2010-04-08 02:19:18 +08:00
]>;
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
// ===---------------------------------------------------------------------===//
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler and will eventually replace itineraries.
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
class A9WriteLMOpsListType<list<WriteSequence> writes> {
list <WriteSequence> Writes = writes;
SchedMachineModel SchedModel = ?;
}
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
// Cortex-A9 machine model for scheduling and other instruction cost heuristics.
def CortexA9Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
Update machine models. Specify buffer sizes for OOO processors. llvm-svn: 184033
2013-06-15 12:50:02 +08:00
let MicroOpBufferSize = 56; // Based on available renamed registers.
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Added MispredictPenalty to SchedMachineModel. This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
2012-08-08 10:44:16 +08:00
let MispredictPenalty = 8; // Based on estimate of pipeline depth.
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
let Itineraries = CortexA9Itineraries;
The Cortex-A9 machine model is incomplete. Mark it as such. Many vector operations never had itineraries. Since the new machine model was a mapping from existing itinerary classes, we don't have a model for these. We still want to migrate A9 even though no one has invested in a complete model, so mark it incomplete to avoid the scheduler asserting. llvm-svn: 198123
2013-12-29 05:57:00 +08:00
// FIXME: Many vector operations were never given an itinerary. We
// haven't mapped these to the new model either.
let CompleteModel = 0;
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
2018-03-19 03:56:15 +08:00
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
}
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available.
New machine model for cortex-a9. Schedule for resources and latency. Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. llvm-svn: 198125
2013-12-29 05:57:05 +08:00
//
// The AGU unit has BufferSize=1 so that the latency between operations
// that use it are considered to stall other operations.
//
// The FP unit has BufferSize=0 so that it is a hard dispatch
// hazard. No instruction may be dispatched while the unit is reserved.
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
let SchedModel = CortexA9Model in {
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9UnitALU : ProcResource<2>;
def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
New machine model for cortex-a9. Schedule for resources and latency. Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. llvm-svn: 198125
2013-12-29 05:57:05 +08:00
def A9UnitAGU : ProcResource<1> { let BufferSize = 1; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9UnitLS : ProcResource<1>;
New machine model for cortex-a9. Schedule for resources and latency. Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. llvm-svn: 198125
2013-12-29 05:57:05 +08:00
def A9UnitFP : ProcResource<1> { let BufferSize = 0; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9UnitB : ProcResource<1>;
//===----------------------------------------------------------------------===//
// Define scheduler read/write types with their resources and latency on A9.
// Consume an issue slot, but no processor resources. This is useful when all
// other writes associated with the operand have NumMicroOps = 0.
def A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
// Write an integer register.
def A9WriteI : SchedWriteRes<[A9UnitALU]>;
// Write an integer shifted-by register
def A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
// Basic ALU.
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def A9WriteALU : SchedWriteRes<[A9UnitALU]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// ALU with operand shifted by immediate.
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// ALU with operand shifted by register.
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def A9WriteALUsr : SchedWriteRes<[A9UnitALU]> { let Latency = 3; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// Multiplication
def A9WriteM : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; }
def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
let NumMicroOps = 0; }
def A9WriteM16 : SchedWriteRes<[A9UnitMul]> { let Latency = 3; }
def A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4;
let NumMicroOps = 0; }
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-03 05:08:12 +08:00
def : SchedAlias<WriteMUL16, A9WriteM16>;
def : SchedAlias<WriteMUL32, A9WriteM>;
def : SchedAlias<WriteMUL64Lo, A9WriteM>;
def : SchedAlias<WriteMUL64Hi, A9WriteMHi>;
def : SchedAlias<WriteMAC16, A9WriteM16>;
def : SchedAlias<WriteMAC32, A9WriteM>;
def : SchedAlias<WriteMAC64Lo, A9WriteM>;
def : SchedAlias<WriteMAC64Hi, A9WriteMHi>;
def : ReadAdvance<ReadMUL, 0>;
def : ReadAdvance<ReadMAC, 0>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// Floating-point
// Only one FP or AGU instruction may issue per cycle. We model this
// by having FP instructions consume the AGU resource.
def A9WriteF : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
def A9WriteFMov : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
def A9WriteFMulS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; }
def A9WriteFMulD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; }
def A9WriteFMAS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 8; }
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-03 05:08:12 +08:00
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9WriteFMAD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; }
Cortex-A9 latency fixes (w/ -schedmodel only). Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
2012-09-21 13:06:40 +08:00
def A9WriteFDivS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 15; }
def A9WriteFDivD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 25; }
def A9WriteFSqrtS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 17; }
def A9WriteFSqrtD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 32; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// NEON has an odd mix of latencies. Simply name the write types by latency.
Cortex-A9 latency fixes (w/ -schedmodel only). Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
2012-09-21 13:06:40 +08:00
def A9WriteV1 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9WriteV2 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 2; }
def A9WriteV3 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 3; }
def A9WriteV4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
def A9WriteV5 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; }
def A9WriteV6 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; }
def A9WriteV7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 7; }
def A9WriteV9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; }
def A9WriteV10 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 10; }
[ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCI This patch adds missing scheds for Neon VLDx/VSTx instructions. This will help one write schedulers easier/faster in the future for ARM sub-targets. Existing models will not affected by this patch. Reviewed by: Renato Golin, Diana Picus Differential Revision: https://reviews.llvm.org/D33120 llvm-svn: 303717
2017-05-24 13:32:48 +08:00
def : WriteRes<WriteVLD1, []>;
def : WriteRes<WriteVLD2, []>;
def : WriteRes<WriteVLD3, []>;
def : WriteRes<WriteVLD4, []>;
def : WriteRes<WriteVST1, []>;
def : WriteRes<WriteVST2, []>;
def : WriteRes<WriteVST3, []>;
def : WriteRes<WriteVST4, []>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// Reserve A9UnitFP for 2 consecutive cycles.
def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 4;
[TableGen][NFC] Make ResourceCycles definitions more explicit. https://reviews.llvm.org/D46356 llvm-svn: 331439
2018-05-03 14:08:47 +08:00
let ResourceCycles = [2, 1];
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
}
def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 7;
[TableGen][NFC] Make ResourceCycles definitions more explicit. https://reviews.llvm.org/D46356 llvm-svn: 331439
2018-05-03 14:08:47 +08:00
let ResourceCycles = [2, 1];
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
}
def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 9;
[TableGen][NFC] Make ResourceCycles definitions more explicit. https://reviews.llvm.org/D46356 llvm-svn: 331439
2018-05-03 14:08:47 +08:00
let ResourceCycles = [2, 1];
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
}
// Branches don't have a def operand but still consume resources.
def A9WriteB : SchedWriteRes<[A9UnitB]>;
// Address generation.
def A9WriteAdr : SchedWriteRes<[A9UnitAGU]> { let NumMicroOps = 0; }
// Load Integer.
def A9WriteL : SchedWriteRes<[A9UnitLS]> { let Latency = 3; }
[ARM] Classification Improvements to ARM Sched-Models. NFCI. This patch adds missing sched classes for Thumb2 instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. These patches should help write schedulers better and faster in the future for ARM sub-targets. Reviewer: Diana Picus Differential Revision: https://reviews.llvm.org/D29953 llvm-svn: 295811
2017-02-22 15:22:57 +08:00
def : SchedAlias<WriteLd, A9WriteL>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// Load the upper 32-bits using the same micro-op.
def A9WriteLHi : SchedWriteRes<[]> { let Latency = 3;
let NumMicroOps = 0; }
// Offset shifted by register.
def A9WriteLsi : SchedWriteRes<[A9UnitLS]> { let Latency = 4; }
// Load (and zero extend) a byte.
def A9WriteLb : SchedWriteRes<[A9UnitLS]> { let Latency = 4; }
def A9WriteLbsi : SchedWriteRes<[A9UnitLS]> { let Latency = 5; }
// Load or Store Float, aligned.
def A9WriteLSfp : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 1; }
// Store Integer.
def A9WriteS : SchedWriteRes<[A9UnitLS]>;
//===----------------------------------------------------------------------===//
// Define resources dynamically for load multiple variants.
// Define helpers for extra latency without consuming resources.
def A9WriteCycle1 : SchedWriteRes<[]> { let Latency = 1; let NumMicroOps = 0; }
foreach NumCycles = 2-8 in {
def A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>;
} // foreach NumCycles
// Define address generation sequences and predicates for 8 flavors of LDMs.
foreach NumAddr = 1-8 in {
// Define A9WriteAdr1-8 as a sequence of A9WriteAdr with additive
// latency for instructions that generate multiple loads or stores.
def A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>;
// Define a predicate to select the LDM based on number of memory addresses.
def A9LMAdr#NumAddr#Pred :
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
2016-06-30 08:01:54 +08:00
SchedPredicate<"(TII->getNumLDMAddresses(*MI)+1)/2 == "#NumAddr>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
} // foreach NumAddr
// Fall-back for unknown LDMs.
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
2016-06-30 08:01:54 +08:00
def A9LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == 0">;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// LDM/VLDM/VLDn address generation latency & resources.
// Dynamically select the A9WriteAdrN sequence using a predicate.
def A9WriteLMAdr : SchedWriteVariant<[
SchedVar<A9LMAdr1Pred, [A9WriteAdr1]>,
SchedVar<A9LMAdr2Pred, [A9WriteAdr2]>,
SchedVar<A9LMAdr3Pred, [A9WriteAdr3]>,
SchedVar<A9LMAdr4Pred, [A9WriteAdr4]>,
SchedVar<A9LMAdr5Pred, [A9WriteAdr5]>,
SchedVar<A9LMAdr6Pred, [A9WriteAdr6]>,
SchedVar<A9LMAdr7Pred, [A9WriteAdr7]>,
SchedVar<A9LMAdr8Pred, [A9WriteAdr8]>,
// For unknown LDM/VLDM/VSTM, assume 2 32-bit registers.
SchedVar<A9LMUnknownPred, [A9WriteAdr2]>]>;
// Define LDM Resources.
// These take no issue resource, so they can be combined with other
// writes like WriteB.
// A9WriteLMLo takes a single LS resource and 2 cycles.
def A9WriteLMLo : SchedWriteRes<[A9UnitLS]> { let Latency = 2;
let NumMicroOps = 0; }
// Assuming aligned access, the upper half of each pair is free with
// the same latency.
def A9WriteLMHi : SchedWriteRes<[]> { let Latency = 2;
let NumMicroOps = 0; }
// Each A9WriteL#N variant adds N cycles of latency without consuming
// additional resources.
foreach NumAddr = 1-8 in {
def A9WriteL#NumAddr : WriteSequence<
[A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
def A9WriteL#NumAddr#Hi : WriteSequence<
[A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
}
//===----------------------------------------------------------------------===//
// LDM: Load multiple into 32-bit integer registers.
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
def A9WriteLMOpsList : A9WriteLMOpsListType<
[A9WriteL1, A9WriteL1Hi,
A9WriteL2, A9WriteL2Hi,
A9WriteL3, A9WriteL3Hi,
A9WriteL4, A9WriteL4Hi,
A9WriteL5, A9WriteL5Hi,
A9WriteL6, A9WriteL6Hi,
A9WriteL7, A9WriteL7Hi,
A9WriteL8, A9WriteL8Hi]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// A9WriteLM variants expand into a pair of writes for each 64-bit
// value loaded. When the number of registers is odd, the last
// A9WriteLnHi is naturally ignored because the instruction has no
// following def operands. These variants take no issue resource, so
// they may need to be part of a WriteSequence that includes A9WriteIssue.
def A9WriteLM : SchedWriteVariant<[
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// For unknown LDMs, define the maximum number of writes, but only
// make the first two consume resources.
SchedVar<A9LMUnknownPred, [A9WriteL1, A9WriteL1Hi,
A9WriteL2, A9WriteL2Hi,
A9WriteL3Hi, A9WriteL3Hi,
A9WriteL4Hi, A9WriteL4Hi,
A9WriteL5Hi, A9WriteL5Hi,
A9WriteL6Hi, A9WriteL6Hi,
A9WriteL7Hi, A9WriteL7Hi,
A9WriteL8Hi, A9WriteL8Hi]>]> {
let Variadic = 1;
}
//===----------------------------------------------------------------------===//
// VFP Load/Store Multiple Variants, and NEON VLDn/VSTn support.
// A9WriteLfpOp is the same as A9WriteLSfp but takes no issue resources
// so can be used in WriteSequences for in single-issue instructions that
// encapsulate multiple loads.
def A9WriteLfpOp : SchedWriteRes<[A9UnitLS, A9UnitFP]> {
let Latency = 1;
let NumMicroOps = 0;
}
foreach NumAddr = 1-8 in {
// Helper for A9WriteLfp1-8: A sequence of fp loads with no micro-ops.
def A9WriteLfp#NumAddr#Seq : WriteSequence<[A9WriteLfpOp], NumAddr>;
// A9WriteLfp1-8 definitions are statically expanded into a sequence of
// A9WriteLfpOps with additive latency that takes a single issue slot.
// Used directly to describe NEON VLDn.
def A9WriteLfp#NumAddr : WriteSequence<
[A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
// A9WriteLfp1-8Mov adds a cycle of latency and FP resource for
// permuting loaded values.
def A9WriteLfp#NumAddr#Mov : WriteSequence<
[A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
} // foreach NumAddr
// Define VLDM/VSTM PreRA resources.
// A9WriteLMfpPreRA are dynamically expanded into the correct
// A9WriteLfp1-8 sequence based on a predicate. This supports the
// preRA VLDM variants in which all 64-bit loads are written to the
// same tuple of either single or double precision registers.
def A9WriteLMfpPreRA : SchedWriteVariant<[
SchedVar<A9LMAdr1Pred, [A9WriteLfp1]>,
SchedVar<A9LMAdr2Pred, [A9WriteLfp2]>,
SchedVar<A9LMAdr3Pred, [A9WriteLfp3]>,
SchedVar<A9LMAdr4Pred, [A9WriteLfp4]>,
SchedVar<A9LMAdr5Pred, [A9WriteLfp5]>,
SchedVar<A9LMAdr6Pred, [A9WriteLfp6]>,
SchedVar<A9LMAdr7Pred, [A9WriteLfp7]>,
SchedVar<A9LMAdr8Pred, [A9WriteLfp8]>,
// For unknown VLDM/VSTM PreRA, assume 2xS registers.
SchedVar<A9LMUnknownPred, [A9WriteLfp2]>]>;
// Define VLDM/VSTM PostRA Resources.
// A9WriteLMfpLo takes a LS and FP resource and one issue slot but no latency.
def A9WriteLMfpLo : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 0; }
foreach NumAddr = 1-8 in {
// Each A9WriteL#N variant adds N cycles of latency without consuming
// additional resources.
def A9WriteLMfp#NumAddr : WriteSequence<
[A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
// Assuming aligned access, the upper half of each pair is free with
// the same latency.
def A9WriteLMfp#NumAddr#Hi : WriteSequence<
[A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
} // foreach NumAddr
// VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a
// pair of writes for each 64-bit data loaded. When the number of
// registers is odd, the last WriteLMfpnHi is naturally ignored because
// the instruction has no following def operands.
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
def A9WriteLMfpPostRAOpsList : A9WriteLMOpsListType<
[A9WriteLMfp1, A9WriteLMfp2, // 0-1
A9WriteLMfp3, A9WriteLMfp4, // 2-3
A9WriteLMfp5, A9WriteLMfp6, // 4-5
A9WriteLMfp7, A9WriteLMfp8, // 6-7
A9WriteLMfp1Hi, // 8-8
A9WriteLMfp2Hi, A9WriteLMfp2Hi, // 9-10
A9WriteLMfp3Hi, A9WriteLMfp3Hi, // 11-12
A9WriteLMfp4Hi, A9WriteLMfp4Hi, // 13-14
A9WriteLMfp5Hi, A9WriteLMfp5Hi, // 15-16
A9WriteLMfp6Hi, A9WriteLMfp6Hi, // 17-18
A9WriteLMfp7Hi, A9WriteLMfp7Hi, // 19-20
A9WriteLMfp8Hi, A9WriteLMfp8Hi]>; // 21-22
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9WriteLMfpPostRA : SchedWriteVariant<[
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
SchedVar<A9LMAdr2Pred, A9WriteLMfpPostRAOpsList.Writes[0-1, 9-10]>,
SchedVar<A9LMAdr3Pred, A9WriteLMfpPostRAOpsList.Writes[0-2, 10-12]>,
SchedVar<A9LMAdr4Pred, A9WriteLMfpPostRAOpsList.Writes[0-3, 11-14]>,
SchedVar<A9LMAdr5Pred, A9WriteLMfpPostRAOpsList.Writes[0-4, 12-16]>,
SchedVar<A9LMAdr6Pred, A9WriteLMfpPostRAOpsList.Writes[0-5, 13-18]>,
SchedVar<A9LMAdr7Pred, A9WriteLMfpPostRAOpsList.Writes[0-6, 14-20]>,
SchedVar<A9LMAdr8Pred, A9WriteLMfpPostRAOpsList.Writes[0-7, 15-22]>,
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// For unknown LDMs, define the maximum number of writes, but only
Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
2013-09-05 01:05:18 +08:00
// make the first two consume resources. We are optimizing for the case
// where the operands are DPRs, and this determines the first eight
// types. The remaining eight types are filled to cover the case
// where the operands are SPRs.
SchedVar<A9LMUnknownPred, [A9WriteLMfp1, A9WriteLMfp2,
A9WriteLMfp3Hi, A9WriteLMfp4Hi,
A9WriteLMfp5Hi, A9WriteLMfp6Hi,
A9WriteLMfp7Hi, A9WriteLMfp8Hi,
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
A9WriteLMfp5Hi, A9WriteLMfp5Hi,
A9WriteLMfp6Hi, A9WriteLMfp6Hi,
A9WriteLMfp7Hi, A9WriteLMfp7Hi,
A9WriteLMfp8Hi, A9WriteLMfp8Hi]>]> {
let Variadic = 1;
}
// Distinguish between our multiple MI-level forms of the same
// VLDM/VSTM instructions.
def A9PreRA : SchedPredicate<
"TargetRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg())">;
def A9PostRA : SchedPredicate<
"TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).getReg())">;
// VLDM represents all destination registers as a single register
// tuple, unlike LDM. So the number of write operands is not variadic.
def A9WriteLMfp : SchedWriteVariant<[
SchedVar<A9PreRA, [A9WriteLMfpPreRA]>,
SchedVar<A9PostRA, [A9WriteLMfpPostRA]>]>;
//===----------------------------------------------------------------------===//
Correct word hyphenations This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471
2013-12-05 13:44:44 +08:00
// Resources for other (non-LDM/VLDM) Variants.
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// These mov immediate writers are unconditionally expanded with
// additive latency.
def A9WriteI2 : WriteSequence<[A9WriteI, A9WriteI]>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def A9WriteI2pc : WriteSequence<[A9WriteI, A9WriteI, WriteALU]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def A9WriteI2ld : WriteSequence<[A9WriteI, A9WriteI, A9WriteL]>;
// Some ALU operations can read loaded integer values one cycle early.
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def A9ReadALU : SchedReadAdvance<1,
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
[A9WriteL, A9WriteLHi, A9WriteLsi, A9WriteLb, A9WriteLbsi,
A9WriteL1, A9WriteL2, A9WriteL3, A9WriteL4,
A9WriteL5, A9WriteL6, A9WriteL7, A9WriteL8,
A9WriteL1Hi, A9WriteL2Hi, A9WriteL3Hi, A9WriteL4Hi,
A9WriteL5Hi, A9WriteL6Hi, A9WriteL7Hi, A9WriteL8Hi]>;
// Read types for operands that are unconditionally read in cycle N
// after the instruction issues, decreases producer latency by N-1.
def A9Read2 : SchedReadAdvance<1>;
def A9Read3 : SchedReadAdvance<2>;
def A9Read4 : SchedReadAdvance<3>;
//===----------------------------------------------------------------------===//
// Map itinerary classes to scheduler read/write resources per operand.
//
// For ARM, we piggyback scheduler resources on the Itinerary classes
// to avoid perturbing the existing instruction definitions.
// This table follows the ARM Cortex-A9 Technical Reference Manuals,
// mostly in order.
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def :ItinRW<[WriteALU], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
IIC_iMVNi,IIC_iMVNsi,
IIC_iCMOVi,IIC_iCMOVr,IIC_iCMOVsi]>;
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def :ItinRW<[WriteALU, A9ReadALU],[IIC_iMVNr]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def :ItinRW<[A9WriteIsr], [IIC_iMOVsr,IIC_iMVNsr,IIC_iCMOVsr]>;
def :ItinRW<[A9WriteI2], [IIC_iMOVix2,IIC_iCMOVix2]>;
def :ItinRW<[A9WriteI2pc], [IIC_iMOVix2addpc]>;
def :ItinRW<[A9WriteI2ld], [IIC_iMOVix2ld]>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def :ItinRW<[WriteALU], [IIC_iBITi,IIC_iBITr,IIC_iUNAr,IIC_iTSTi,IIC_iTSTr]>;
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def :ItinRW<[WriteALU, A9ReadALU], [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi]>;
def :ItinRW<[WriteALU, A9ReadALU, A9ReadALU],[IIC_iALUr,IIC_iCMPr]>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def :ItinRW<[WriteALUsi], [IIC_iBITsi,IIC_iUNAsi,IIC_iEXTr,IIC_iTSTsi]>;
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def :ItinRW<[WriteALUsi, A9ReadALU], [IIC_iALUsi]>;
def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def :ItinRW<[A9WriteALUsr], [IIC_iBITsr,IIC_iTSTsr,IIC_iEXTAr,IIC_iEXTAsr]>;
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def :ItinRW<[A9WriteALUsr, A9ReadALU], [IIC_iALUsr,IIC_iCMPsr]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// A9WriteHi ignored for MUL32.
def :ItinRW<[A9WriteM, A9WriteMHi], [IIC_iMUL32,IIC_iMAC32,
IIC_iMUL64,IIC_iMAC64]>;
// FIXME: SMLALxx needs itin classes
def :ItinRW<[A9WriteM16, A9WriteM16Hi], [IIC_iMUL16,IIC_iMAC16]>;
// TODO: For floating-point ops, we model the pipeline forwarding
// latencies here. WAW latencies are sometimes longer.
def :ItinRW<[A9WriteFMov], [IIC_fpSTAT, IIC_fpMOVIS, IIC_fpMOVID, IIC_fpMOVSI,
IIC_fpUNA32, IIC_fpUNA64,
IIC_fpCMP32, IIC_fpCMP64]>;
def :ItinRW<[A9WriteFMov, A9WriteFMov], [IIC_fpMOVDI]>;
def :ItinRW<[A9WriteF], [IIC_fpCVTSD, IIC_fpCVTDS, IIC_fpCVTSH, IIC_fpCVTHS,
IIC_fpCVTIS, IIC_fpCVTID, IIC_fpCVTSI, IIC_fpCVTDI,
IIC_fpALU32, IIC_fpALU64]>;
def :ItinRW<[A9WriteFMulS], [IIC_fpMUL32]>;
def :ItinRW<[A9WriteFMulD], [IIC_fpMUL64]>;
def :ItinRW<[A9WriteFMAS], [IIC_fpMAC32]>;
def :ItinRW<[A9WriteFMAD], [IIC_fpMAC64]>;
def :ItinRW<[A9WriteFDivS], [IIC_fpDIV32]>;
def :ItinRW<[A9WriteFDivD], [IIC_fpDIV64]>;
def :ItinRW<[A9WriteFSqrtS], [IIC_fpSQRT32]>;
def :ItinRW<[A9WriteFSqrtD], [IIC_fpSQRT64]>;
def :ItinRW<[A9WriteB], [IIC_Br]>;
// A9 PLD is processed in a dedicated unit.
def :ItinRW<[], [IIC_Preload]>;
// Note: We must assume that loads are aligned, since the machine
// model cannot know this statically and A9 ignores alignment hints.
// A9WriteAdr consumes AGU regardless address writeback. But it's
// latency is only relevant for users of an updated address.
def :ItinRW<[A9WriteL, A9WriteAdr], [IIC_iLoad_i,IIC_iLoad_r,
IIC_iLoad_iu,IIC_iLoad_ru]>;
def :ItinRW<[A9WriteLsi, A9WriteAdr], [IIC_iLoad_si,IIC_iLoad_siu]>;
def :ItinRW<[A9WriteLb, A9WriteAdr2], [IIC_iLoad_bh_i,IIC_iLoad_bh_r,
IIC_iLoad_bh_iu,IIC_iLoad_bh_ru]>;
def :ItinRW<[A9WriteLbsi, A9WriteAdr2], [IIC_iLoad_bh_si,IIC_iLoad_bh_siu]>;
def :ItinRW<[A9WriteL, A9WriteLHi, A9WriteAdr], [IIC_iLoad_d_i,IIC_iLoad_d_r,
IIC_iLoad_d_ru]>;
// Store either has no def operands, or the one def for address writeback.
def :ItinRW<[A9WriteAdr, A9WriteS], [IIC_iStore_i, IIC_iStore_r,
IIC_iStore_iu, IIC_iStore_ru,
IIC_iStore_d_i, IIC_iStore_d_r,
IIC_iStore_d_ru]>;
def :ItinRW<[A9WriteAdr2, A9WriteS], [IIC_iStore_si, IIC_iStore_siu,
IIC_iStore_bh_i, IIC_iStore_bh_r,
IIC_iStore_bh_iu, IIC_iStore_bh_ru]>;
def :ItinRW<[A9WriteAdr3, A9WriteS], [IIC_iStore_bh_si, IIC_iStore_bh_siu]>;
// A9WriteML will be expanded into a separate write for each def
// operand. Address generation consumes resources, but A9WriteLMAdr
// is listed after all def operands, so has no effective latency.
//
// Note: A9WriteLM expands into an even number of def operands. The
// actual number of def operands may be less by one.
def :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteIssue], [IIC_iLoad_m, IIC_iPop]>;
// Load multiple with address writeback has an extra def operand in
// front of the loaded registers.
//
// Reuse the load-multiple variants for store-multiple because the
// resources are identical, For stores only the address writeback
// has a def operand so the WriteL latencies are unused.
def :ItinRW<[A9WriteLMAdr, A9WriteLM, A9WriteIssue], [IIC_iLoad_mu,
IIC_iStore_m,
IIC_iStore_mu]>;
def :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteB], [IIC_iLoad_mBr, IIC_iPop_Br]>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def :ItinRW<[A9WriteL, A9WriteAdr, WriteALU], [IIC_iLoadiALU]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def :ItinRW<[A9WriteLSfp, A9WriteAdr], [IIC_fpLoad32, IIC_fpLoad64]>;
def :ItinRW<[A9WriteLMfp, A9WriteLMAdr], [IIC_fpLoad_m]>;
def :ItinRW<[A9WriteLMAdr, A9WriteLMfp], [IIC_fpLoad_mu]>;
def :ItinRW<[A9WriteAdr, A9WriteLSfp], [IIC_fpStore32, IIC_fpStore64,
IIC_fpStore_m, IIC_fpStore_mu]>;
// Note: Unlike VLDM, VLD1 expects the writeback operand after the
// normal writes.
def :ItinRW<[A9WriteLfp1, A9WriteAdr1], [IIC_VLD1, IIC_VLD1u,
IIC_VLD1x2, IIC_VLD1x2u]>;
def :ItinRW<[A9WriteLfp2, A9WriteAdr2], [IIC_VLD1x3, IIC_VLD1x3u,
IIC_VLD1x4, IIC_VLD1x4u,
IIC_VLD4dup, IIC_VLD4dupu]>;
def :ItinRW<[A9WriteLfp1Mov, A9WriteAdr1], [IIC_VLD1dup, IIC_VLD1dupu,
IIC_VLD2, IIC_VLD2u,
IIC_VLD2dup, IIC_VLD2dupu]>;
def :ItinRW<[A9WriteLfp2Mov, A9WriteAdr1], [IIC_VLD1ln, IIC_VLD1lnu,
IIC_VLD2x2, IIC_VLD2x2u,
IIC_VLD2ln, IIC_VLD2lnu]>;
def :ItinRW<[A9WriteLfp3Mov, A9WriteAdr3], [IIC_VLD3, IIC_VLD3u,
IIC_VLD3dup, IIC_VLD3dupu]>;
def :ItinRW<[A9WriteLfp4Mov, A9WriteAdr4], [IIC_VLD4, IIC_VLD4u,
IIC_VLD4ln, IIC_VLD4lnu]>;
def :ItinRW<[A9WriteLfp5Mov, A9WriteAdr5], [IIC_VLD3ln, IIC_VLD3lnu]>;
// Vector stores use similar resources to vector loads, so use the
// same write types. The address write must be first for stores with
// address writeback.
def :ItinRW<[A9WriteAdr1, A9WriteLfp1], [IIC_VST1, IIC_VST1u,
IIC_VST1x2, IIC_VST1x2u,
IIC_VST1ln, IIC_VST1lnu,
IIC_VST2, IIC_VST2u,
IIC_VST2x2, IIC_VST2x2u,
IIC_VST2ln, IIC_VST2lnu]>;
def :ItinRW<[A9WriteAdr2, A9WriteLfp2], [IIC_VST1x3, IIC_VST1x3u,
IIC_VST1x4, IIC_VST1x4u,
IIC_VST3, IIC_VST3u,
IIC_VST3ln, IIC_VST3lnu,
IIC_VST4, IIC_VST4u,
IIC_VST4ln, IIC_VST4lnu]>;
// NEON moves.
def :ItinRW<[A9WriteV2], [IIC_VMOVSI, IIC_VMOVDI, IIC_VMOVD, IIC_VMOVQ]>;
def :ItinRW<[A9WriteV1], [IIC_VMOV, IIC_VMOVIS, IIC_VMOVID]>;
def :ItinRW<[A9WriteV3], [IIC_VMOVISL, IIC_VMOVN]>;
// NEON integer arithmetic
//
// VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
def :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VBINiD, IIC_VBINiQ]>;
// VSUB/VMVN/VCLSD/VCLZD/VCNTD
def :ItinRW<[A9WriteV3, A9Read2], [IIC_VSUBiD, IIC_VSUBiQ, IIC_VCNTiD]>;
// VADDL/VSUBL/VNEG are mapped later under IIC_SHLi.
// ...
// VHADD/VRHADD/VQADD/VTST/VADH/VRADH
def :ItinRW<[A9WriteV4, A9Read2, A9Read2], [IIC_VBINi4D, IIC_VBINi4Q]>;
The Cortex-A9 machine model is incomplete. Mark it as such. Many vector operations never had itineraries. Since the new machine model was a mapping from existing itinerary classes, we don't have a model for these. We still want to migrate A9 even though no one has invested in a complete model, so mark it incomplete to avoid the scheduler asserting. llvm-svn: 198123
2013-12-29 05:57:00 +08:00
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
def :ItinRW<[A9WriteV4, A9Read2], [IIC_VSUBi4D, IIC_VSUBi4Q]>;
// VQNEG/VQABS
def :ItinRW<[A9WriteV4], [IIC_VQUNAiD, IIC_VQUNAiQ]>;
// VABS
def :ItinRW<[A9WriteV4, A9Read2], [IIC_VUNAiD, IIC_VUNAiQ]>;
// VPADD/VPADDL are mapped later under IIC_SHLi.
// ...
// VCLSQ/VCLZQ/VCNTQ, takes two cycles.
def :ItinRW<[A9Write2V4, A9Read3], [IIC_VCNTiQ]>;
// VMOVimm/VMVNimm/VORRimm/VBICimm
def :ItinRW<[A9WriteV3], [IIC_VMOVImm]>;
def :ItinRW<[A9WriteV6, A9Read3, A9Read2], [IIC_VABAD, IIC_VABAQ]>;
def :ItinRW<[A9WriteV6, A9Read3], [IIC_VPALiD, IIC_VPALiQ]>;
// NEON integer multiply
//
// Note: these don't quite match the timing docs, but they do match
// the original A9 itinerary.
def :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VMULi16D]>;
def :ItinRW<[A9WriteV7, A9Read2, A9Read2], [IIC_VMULi16Q]>;
def :ItinRW<[A9Write2V7, A9Read2], [IIC_VMULi32D]>;
def :ItinRW<[A9Write2V9, A9Read2], [IIC_VMULi32Q]>;
def :ItinRW<[A9WriteV6, A9Read3, A9Read2, A9Read2], [IIC_VMACi16D]>;
def :ItinRW<[A9WriteV7, A9Read3, A9Read2, A9Read2], [IIC_VMACi16Q]>;
def :ItinRW<[A9Write2V7, A9Read3, A9Read2], [IIC_VMACi32D]>;
def :ItinRW<[A9Write2V9, A9Read3, A9Read2], [IIC_VMACi32Q]>;
// NEON integer shift
// TODO: Q,Q,Q shifts should actually reserve FP for 2 cycles.
def :ItinRW<[A9WriteV3], [IIC_VSHLiD, IIC_VSHLiQ]>;
def :ItinRW<[A9WriteV4], [IIC_VSHLi4D, IIC_VSHLi4Q]>;
// NEON permute
Fix the A9 machine model. VTRN writes two registers. llvm-svn: 196514
2013-12-06 01:55:49 +08:00
def :ItinRW<[A9WriteV2, A9WriteV2], [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD]>;
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
def :ItinRW<[A9WriteV3, A9WriteV4, ReadDefault, A9Read2],
[IIC_VPERMQ3, IIC_VEXTQ]>;
def :ItinRW<[A9WriteV3, A9Read2], [IIC_VTB1]>;
def :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VTB2]>;
def :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3], [IIC_VTB3]>;
def :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3, A9Read3], [IIC_VTB4]>;
def :ItinRW<[A9WriteV3, ReadDefault, A9Read2], [IIC_VTBX1]>;
def :ItinRW<[A9WriteV3, ReadDefault, A9Read2, A9Read2], [IIC_VTBX2]>;
def :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3], [IIC_VTBX3]>;
def :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3, A9Read3],
[IIC_VTBX4]>;
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
// NEON floating-point
def :ItinRW<[A9WriteV5, A9Read2, A9Read2], [IIC_VBIND]>;
def :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VBINQ]>;
def :ItinRW<[A9WriteV5, A9Read2], [IIC_VUNAD, IIC_VFMULD]>;
def :ItinRW<[A9WriteV6, A9Read2], [IIC_VUNAQ, IIC_VFMULQ]>;
def :ItinRW<[A9WriteV9, A9Read3, A9Read2], [IIC_VMACD, IIC_VFMACD]>;
def :ItinRW<[A9WriteV10, A9Read3, A9Read2], [IIC_VMACQ, IIC_VFMACQ]>;
def :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>;
def :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
// Map SchedRWs that are identical for cortexa9 to existing resources.
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def : SchedAlias<WriteALU, A9WriteALU>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
def : SchedAlias<WriteALUsr, A9WriteALUsr>;
def : SchedAlias<WriteALUSsr, A9WriteALUsr>;
def : SchedAlias<ReadALU, A9ReadALU>;
def : SchedAlias<ReadALUsr, A9ReadALU>;
[ARM] Classification Improvements to ARM Sched-Models. NFCI. This patch adds missing sched classes for Thumb2 instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. These patches should help write schedulers better and faster in the future for ARM sub-targets. Reviewer: Diana Picus Differential Revision: https://reviews.llvm.org/D29953 llvm-svn: 295811
2017-02-22 15:22:57 +08:00
def : SchedAlias<WriteST, A9WriteS>;
[ARM] Classification Improvements to ARM Sched-Models. NFCI. This is a series of patches to enable adding of machine sched models for ARM processors easier and compact. They define new sched-readwrites for groups of ARM instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. The current patch focuses on floating-point instructions. Reviewers: Diana Picus (rovka), Renato Golin (rengolin) Differential Revision: https://reviews.llvm.org/D28194 llvm-svn: 292825
2017-01-24 04:20:39 +08:00
// ===---------------------------------------------------------------------===//
// Floating-point. Map target defined SchedReadWrite to processor specific ones
//
def : WriteRes<WriteFPCVT, [A9UnitFP, A9UnitAGU]> { let Latency = 4; }
def : SchedAlias<WriteFPMOV, A9WriteFMov>;
def : SchedAlias<WriteFPALU32, A9WriteF>;
def : SchedAlias<WriteFPALU64, A9WriteF>;
def : SchedAlias<WriteFPMUL32, A9WriteFMulS>;
def : SchedAlias<WriteFPMUL64, A9WriteFMulD>;
def : SchedAlias<WriteFPMAC32, A9WriteFMAS>;
def : SchedAlias<WriteFPMAC64, A9WriteFMAD>;
def : SchedAlias<WriteFPDIV32, A9WriteFDivS>;
def : SchedAlias<WriteFPDIV64, A9WriteFDivD>;
def : SchedAlias<WriteFPSQRT32, A9WriteFSqrtS>;
def : SchedAlias<WriteFPSQRT64, A9WriteFSqrtD>;
def : ReadAdvance<ReadFPMUL, 0>;
def : ReadAdvance<ReadFPMAC, 0>;
// ===---------------------------------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types.
//
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def : InstRW< [WriteALU],
(instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr",
"BICrr")>;
def : InstRW< [WriteALUsi], (instregex "ANDrsi", "ORRrsi", "EORrsi", "BICrsi")>;
def : InstRW< [WriteALUsr], (instregex "ANDrsr", "ORRrsr", "EORrsr", "BICrsr")>;
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 21:07:05 +08:00
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 13:01:06 +08:00
def : SchedAlias<WriteCMP, A9WriteALU>;
def : SchedAlias<WriteCMPsi, A9WriteALU>;
def : SchedAlias<WriteCMPsr, A9WriteALU>;
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi",
"MOVCCsr")>;
def : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>;
[ARM] Remove sched model instregex entries that don't match any instructions (D44687) Reviewed by @javed.absar llvm-svn: 328457
2018-03-26 03:07:17 +08:00
def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm")>;
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>;
def : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>;
def : InstRW< [WriteALU], (instregex "SEL")>;
def : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>;
def : InstRW< [A9WriteM],
(instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
"SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>;
def : InstRW< [A9WriteM, A9WriteMHi],
(instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
[ARM] Remove sched model instregex entries that don't match any instructions (D44687) Reviewed by @javed.absar llvm-svn: 328457
2018-03-26 03:07:17 +08:00
"UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB",
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
"SMLALTT")>;
// FIXME: These instructions used to have NoItinerary. Just copied the one from above.
def : InstRW< [A9WriteM, A9WriteMHi],
(instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX",
[ARM] Remove sched model instregex entries that don't match any instructions (D44687) Reviewed by @javed.absar llvm-svn: 328457
2018-03-26 03:07:17 +08:00
"SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
ARM sched model: Cortex A9 - More InstRW sched resources Add more InstRW mappings. Reapply 183266. llvm-svn: 183435
2013-06-07 03:30:21 +08:00
def : InstRW<[A9WriteM16, A9WriteM16Hi],
(instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>;
def : InstRW<[A9WriteM16, A9WriteM16Hi],
(instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT")>;
def : InstRW<[A9WriteL], (instregex "LDRi12", "PICLDR$")>;
def : InstRW<[A9WriteLsi], (instregex "LDRrs")>;
def : InstRW<[A9WriteLb],
(instregex "LDRBi12", "PICLDRH", "PICLDRB", "PICLDRSH", "PICLDRSB",
"LDRH", "LDRSH", "LDRSB")>;
def : InstRW<[A9WriteLbsi], (instregex "LDRrs")>;
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-03 05:08:12 +08:00
def : WriteRes<WriteDIV, []> { let Latency = 0; }
ARM sched model: Add divsion, loads, branches, vfp cvt Add some generic SchedWrites and assign resources for Swift and Cortex A9. Reapply of r183257. (Removed empty InstRW for division on swift) llvm-svn: 183319
2013-06-06 00:06:11 +08:00
def : WriteRes<WriteBr, [A9UnitB]>;
def : WriteRes<WriteBrL, [A9UnitB]>;
def : WriteRes<WriteBrTbl, [A9UnitB]>;
def : WriteRes<WritePreLd, []>;
ARM sched model: Add integer VFP/SIMD instructions on Swift Reapply 183269. llvm-svn: 183441
2013-06-07 04:26:18 +08:00
def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
Cortex-A9 instruction-level scheduling machine model. This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
2012-09-15 02:31:58 +08:00
} // SchedModel = CortexA9Model