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llvm-project/llvm/test/CodeGen/AArch64/cmp-const-max.ll

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[AArch64] Register passes so they can be run by llc Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
2016-08-01 13:56:57 +08:00
; RUN: llc -verify-machineinstrs -aarch64-enable-atomic-cfg-tidy=0 < %s -mtriple=aarch64-none-eabihf -fast-isel=false | FileCheck %s
[AArch64] Fix miscompile of comparison with 0xffffffffffffffff Some literals in the AArch64 backend had 15 'f's rather than 16, causing comparisons with a constant 0xffffffffffffffff to be miscompiled. llvm-svn: 221157
2014-11-03 23:28:40 +08:00
define i32 @ule_64_max(i64 %p) {
entry:
; CHECK-LABEL: ule_64_max:
; CHECK: cmn x0, #1
; CHECK: b.hi [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
%cmp = icmp ule i64 %p, 18446744073709551615 ; 0xffffffffffffffff
br i1 %cmp, label %ret_one, label %ret_zero
ret_one:
ret i32 1
ret_zero:
; CHECK: [[RET_ZERO]]:
; CHECK-NEXT: mov w0, wzr
ret i32 0
}
define i32 @ugt_64_max(i64 %p) {
entry:
; CHECK-LABEL: ugt_64_max:
; CHECK: cmn x0, #1
; CHECK: b.ls [[RET_ZERO:.LBB[0-9]+_[0-9]+]]
%cmp = icmp ugt i64 %p, 18446744073709551615 ; 0xffffffffffffffff
br i1 %cmp, label %ret_one, label %ret_zero
ret_one:
ret i32 1
ret_zero:
; CHECK: [[RET_ZERO]]:
; CHECK-NEXT: mov w0, wzr
ret i32 0
}