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llvm-project/llvm/test/CodeGen/AArch64/arm64-narrow-st-merge.ll

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[AArch64] Enable merging of adjacent zero stores for all subtargets. This optimization merges adjacent zero stores into a wider store. e.g., strh wzr, [x0] strh wzr, [x0, #2] ; becomes str wzr, [x0] e.g., str wzr, [x0] str wzr, [x0, #4] ; becomes str xzr, [x0] Previously, this was only enabled for Kryo and Cortex-A57. Differential Revision: https://reviews.llvm.org/D26396 llvm-svn: 286592
2016-11-11 22:10:12 +08:00
; RUN: llc < %s -mtriple aarch64--none-eabi -verify-machineinstrs | FileCheck %s
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; RUN: llc < %s -mtriple aarch64--none-eabi -mattr=+strict-align -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-STRICT
[AArch64]Extend merging narrow loads into a wider load This change extends r251438 to handle more narrow load promotions including byte type, unscaled, and signed. For example, this change will convert : ldursh w1, [x0, #-2] ldurh w2, [x0, #-4] into ldur w2, [x0, #-4] asr w1, w2, #16 and w2, w2, #0xffff llvm-svn: 253577
2015-11-20 01:21:41 +08:00
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
; CHECK-LABEL: Strh_zero
; CHECK: str wzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Strh_zero
; CHECK-STRICT: strh wzr
; CHECK-STRICT: strh wzr
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
define void @Strh_zero(i16* nocapture %P, i32 %n) {
entry:
[AArch64] Removed the narrow load merging code in the ld/st optimizer. This feature has been disabled for some time now, so remove cruft. Differential Revision: https://reviews.llvm.org/D26248 llvm-svn: 286110
2016-11-07 23:27:22 +08:00
%idxprom = sext i32 %n to i64
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
%arrayidx = getelementptr inbounds i16, i16* %P, i64 %idxprom
[AArch64] Removed the narrow load merging code in the ld/st optimizer. This feature has been disabled for some time now, so remove cruft. Differential Revision: https://reviews.llvm.org/D26248 llvm-svn: 286110
2016-11-07 23:27:22 +08:00
store i16 0, i16* %arrayidx
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
%add = add nsw i32 %n, 1
%idxprom1 = sext i32 %add to i64
%arrayidx2 = getelementptr inbounds i16, i16* %P, i64 %idxprom1
store i16 0, i16* %arrayidx2
ret void
}
; CHECK-LABEL: Strh_zero_4
[ARM][AArch64][DAG] Reenable post-legalize store merge Reenable post-legalize stores with constant merging computation and corresponding test case. * Properly truncate store merge constants * Disable merging of truncated stores floating points * Ensure merges of constant stores into a single vector are constructed from legal elements. Reviewers: eastig, efriedma Reviewed By: eastig Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319899
2017-12-06 23:30:13 +08:00
; CHECK: str xzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Strh_zero_4
; CHECK-STRICT: strh wzr
; CHECK-STRICT: strh wzr
; CHECK-STRICT: strh wzr
; CHECK-STRICT: strh wzr
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
define void @Strh_zero_4(i16* nocapture %P, i32 %n) {
entry:
%idxprom = sext i32 %n to i64
%arrayidx = getelementptr inbounds i16, i16* %P, i64 %idxprom
store i16 0, i16* %arrayidx
%add = add nsw i32 %n, 1
%idxprom1 = sext i32 %add to i64
%arrayidx2 = getelementptr inbounds i16, i16* %P, i64 %idxprom1
store i16 0, i16* %arrayidx2
%add3 = add nsw i32 %n, 2
%idxprom4 = sext i32 %add3 to i64
%arrayidx5 = getelementptr inbounds i16, i16* %P, i64 %idxprom4
store i16 0, i16* %arrayidx5
%add6 = add nsw i32 %n, 3
%idxprom7 = sext i32 %add6 to i64
%arrayidx8 = getelementptr inbounds i16, i16* %P, i64 %idxprom7
store i16 0, i16* %arrayidx8
ret void
}
[AArch64] Handle missing store pair opportunity Summary: This change will handle missing store pair opportunity where the first store instruction stores zero followed by the non-zero store. For example, this change will convert : str wzr, [x8] str w1, [x8, #4] into: stp wzr, w1, [x8] Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18570 llvm-svn: 265021
2016-03-31 22:47:24 +08:00
; CHECK-LABEL: Strw_zero
; CHECK: str xzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Strw_zero
; CHECK-STRICT: stp wzr, wzr
[AArch64] Merge two adjacent str WZR into str XZR Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
2016-02-12 23:25:39 +08:00
define void @Strw_zero(i32* nocapture %P, i32 %n) {
entry:
%idxprom = sext i32 %n to i64
%arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
store i32 0, i32* %arrayidx
%add = add nsw i32 %n, 1
%idxprom1 = sext i32 %add to i64
%arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1
store i32 0, i32* %arrayidx2
ret void
}
[AArch64] Handle missing store pair opportunity Summary: This change will handle missing store pair opportunity where the first store instruction stores zero followed by the non-zero store. For example, this change will convert : str wzr, [x8] str w1, [x8, #4] into: stp wzr, w1, [x8] Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18570 llvm-svn: 265021
2016-03-31 22:47:24 +08:00
; CHECK-LABEL: Strw_zero_nonzero
; CHECK: stp wzr, w1
define void @Strw_zero_nonzero(i32* nocapture %P, i32 %n) {
entry:
%idxprom = sext i32 %n to i64
%arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
store i32 0, i32* %arrayidx
%add = add nsw i32 %n, 1
%idxprom1 = sext i32 %add to i64
%arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1
store i32 %n, i32* %arrayidx2
ret void
}
; CHECK-LABEL: Strw_zero_4
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK: stp xzr, xzr
; CHECK-STRICT-LABEL: Strw_zero_4
; CHECK-STRICT: stp wzr, wzr
; CHECK-STRICT: stp wzr, wzr
[AArch64] Merge two adjacent str WZR into str XZR Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
2016-02-12 23:25:39 +08:00
define void @Strw_zero_4(i32* nocapture %P, i32 %n) {
entry:
%idxprom = sext i32 %n to i64
%arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
store i32 0, i32* %arrayidx
%add = add nsw i32 %n, 1
%idxprom1 = sext i32 %add to i64
%arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1
store i32 0, i32* %arrayidx2
%add3 = add nsw i32 %n, 2
%idxprom4 = sext i32 %add3 to i64
%arrayidx5 = getelementptr inbounds i32, i32* %P, i64 %idxprom4
store i32 0, i32* %arrayidx5
%add6 = add nsw i32 %n, 3
%idxprom7 = sext i32 %add6 to i64
%arrayidx8 = getelementptr inbounds i32, i32* %P, i64 %idxprom7
store i32 0, i32* %arrayidx8
ret void
}
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
; CHECK-LABEL: Sturb_zero
; CHECK: sturh wzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Sturb_zero
; CHECK-STRICT: sturb wzr
; CHECK-STRICT: sturb wzr
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
define void @Sturb_zero(i8* nocapture %P, i32 %n) #0 {
entry:
%sub = add nsw i32 %n, -2
%idxprom = sext i32 %sub to i64
%arrayidx = getelementptr inbounds i8, i8* %P, i64 %idxprom
store i8 0, i8* %arrayidx
%sub2= add nsw i32 %n, -1
%idxprom1 = sext i32 %sub2 to i64
%arrayidx2 = getelementptr inbounds i8, i8* %P, i64 %idxprom1
store i8 0, i8* %arrayidx2
ret void
}
; CHECK-LABEL: Sturh_zero
; CHECK: stur wzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Sturh_zero
; CHECK-STRICT: sturh wzr
; CHECK-STRICT: sturh wzr
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
define void @Sturh_zero(i16* nocapture %P, i32 %n) {
entry:
%sub = add nsw i32 %n, -2
%idxprom = sext i32 %sub to i64
%arrayidx = getelementptr inbounds i16, i16* %P, i64 %idxprom
store i16 0, i16* %arrayidx
%sub1 = add nsw i32 %n, -3
%idxprom2 = sext i32 %sub1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %P, i64 %idxprom2
store i16 0, i16* %arrayidx3
ret void
}
; CHECK-LABEL: Sturh_zero_4
[ARM][AArch64][DAG] Reenable post-legalize store merge Reenable post-legalize stores with constant merging computation and corresponding test case. * Properly truncate store merge constants * Disable merging of truncated stores floating points * Ensure merges of constant stores into a single vector are constructed from legal elements. Reviewers: eastig, efriedma Reviewed By: eastig Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319899
2017-12-06 23:30:13 +08:00
; CHECK: stur xzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Sturh_zero_4
; CHECK-STRICT: sturh wzr
; CHECK-STRICT: sturh wzr
; CHECK-STRICT: sturh wzr
; CHECK-STRICT: sturh wzr
[AArch64]Merge narrow zero stores to a wider store This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
2015-11-21 05:14:07 +08:00
define void @Sturh_zero_4(i16* nocapture %P, i32 %n) {
entry:
%sub = add nsw i32 %n, -3
%idxprom = sext i32 %sub to i64
%arrayidx = getelementptr inbounds i16, i16* %P, i64 %idxprom
store i16 0, i16* %arrayidx
%sub1 = add nsw i32 %n, -4
%idxprom2 = sext i32 %sub1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %P, i64 %idxprom2
store i16 0, i16* %arrayidx3
%sub4 = add nsw i32 %n, -2
%idxprom5 = sext i32 %sub4 to i64
%arrayidx6 = getelementptr inbounds i16, i16* %P, i64 %idxprom5
store i16 0, i16* %arrayidx6
%sub7 = add nsw i32 %n, -1
%idxprom8 = sext i32 %sub7 to i64
%arrayidx9 = getelementptr inbounds i16, i16* %P, i64 %idxprom8
store i16 0, i16* %arrayidx9
ret void
}
[AArch64] Merge two adjacent str WZR into str XZR Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
2016-02-12 23:25:39 +08:00
[AArch64] Handle missing store pair opportunity Summary: This change will handle missing store pair opportunity where the first store instruction stores zero followed by the non-zero store. For example, this change will convert : str wzr, [x8] str w1, [x8, #4] into: stp wzr, w1, [x8] Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18570 llvm-svn: 265021
2016-03-31 22:47:24 +08:00
; CHECK-LABEL: Sturw_zero
; CHECK: stur xzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Sturw_zero
; CHECK-STRICT: stp wzr, wzr
[AArch64] Merge two adjacent str WZR into str XZR Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
2016-02-12 23:25:39 +08:00
define void @Sturw_zero(i32* nocapture %P, i32 %n) {
entry:
%sub = add nsw i32 %n, -3
%idxprom = sext i32 %sub to i64
%arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
store i32 0, i32* %arrayidx
%sub1 = add nsw i32 %n, -4
%idxprom2 = sext i32 %sub1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %P, i64 %idxprom2
store i32 0, i32* %arrayidx3
ret void
}
[AArch64] Handle missing store pair opportunity Summary: This change will handle missing store pair opportunity where the first store instruction stores zero followed by the non-zero store. For example, this change will convert : str wzr, [x8] str w1, [x8, #4] into: stp wzr, w1, [x8] Reviewers: jmolloy, t.p.northover, mcrosier Subscribers: flyingforyou, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18570 llvm-svn: 265021
2016-03-31 22:47:24 +08:00
; CHECK-LABEL: Sturw_zero_4
; CHECK: stp xzr, xzr
[AArch64] Add test to show narrow zero store merging is disabled with strict align. NFC. llvm-svn: 286617
2016-11-12 03:25:48 +08:00
; CHECK-STRICT-LABEL: Sturw_zero_4
; CHECK-STRICT: stp wzr, wzr
; CHECK-STRICT: stp wzr, wzr
[AArch64] Merge two adjacent str WZR into str XZR Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
2016-02-12 23:25:39 +08:00
define void @Sturw_zero_4(i32* nocapture %P, i32 %n) {
entry:
%sub = add nsw i32 %n, -3
%idxprom = sext i32 %sub to i64
%arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom
store i32 0, i32* %arrayidx
%sub1 = add nsw i32 %n, -4
%idxprom2 = sext i32 %sub1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %P, i64 %idxprom2
store i32 0, i32* %arrayidx3
%sub4 = add nsw i32 %n, -2
%idxprom5 = sext i32 %sub4 to i64
%arrayidx6 = getelementptr inbounds i32, i32* %P, i64 %idxprom5
store i32 0, i32* %arrayidx6
%sub7 = add nsw i32 %n, -1
%idxprom8 = sext i32 %sub7 to i64
%arrayidx9 = getelementptr inbounds i32, i32* %P, i64 %idxprom8
store i32 0, i32* %arrayidx9
ret void
}