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llvm-project/llvm/test/CodeGen/X86/vec_int_to_fp.ll

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[X86][AVX512] Autoupgrade lossless i32/u32 to f64 conversion intrinsics with generic IR Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic SINT_TO_FP/UINT_TO_FP calls instead of x86 intrinsics without affecting final codegen. LLVM counterpart to D26686 Differential Revision: https://reviews.llvm.org/D26736 llvm-svn: 287108
2016-11-16 22:48:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Added 32-bit builds to fp<->int tests. Ensure that i686 x87/SSE/SSE2 targets all build. llvm-svn: 241368
2015-07-04 04:07:57 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=VEX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=VEX --check-prefix=AVX2
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512VL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512VLDQ
[X86] Added 32-bit builds to fp<->int tests. Ensure that i686 x87/SSE/SSE2 targets all build. llvm-svn: 241368
2015-07-04 04:07:57 +08:00
;
; 32-bit tests to make sure we're not doing anything stupid.
; RUN: llc < %s -mtriple=i686-unknown-unknown
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
; Signed Integer to Double
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @sitofp_2i64_to_2f64(<2 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_2i64_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: cvtsi2sdq %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; VEX-LABEL: sitofp_2i64_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; VEX-NEXT: retq
;
; AVX512F-LABEL: sitofp_2i64_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_2i64_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: sitofp_2i64_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vpextrq $1, %xmm0, %rax
; AVX512DQ-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512DQ-NEXT: vmovq %xmm0, %rax
; AVX512DQ-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512DQ-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_2i64_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = sitofp <2 x i64> %a to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @sitofp_2i32_to_2f64(<4 x i32> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_2i32_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_2i32_to_2f64:
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
; AVX: # BB#0:
[X86][SSE] Vectorize v2i32 to v2f64 conversions This patch enables support for the conversion of v2i32 to v2f64 to use the CVTDQ2PD xmm instruction and stay on the SSE unit instead of scalarizing, sign extending to i64 and using CVTSI2SDQ scalar conversions. Differential Revision: http://reviews.llvm.org/D10433 llvm-svn: 239855
2015-06-17 05:40:28 +08:00
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
; AVX-NEXT: retq
%shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i32> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @sitofp_4i32_to_2f64(<4 x i32> %a) {
; SSE-LABEL: sitofp_4i32_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: sitofp_4i32_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vcvtdq2pd %xmm0, %ymm0
; VEX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; VEX-NEXT: vzeroupper
; VEX-NEXT: retq
;
; AVX512-LABEL: sitofp_4i32_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <4 x i32> %a to <4 x double>
%shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @sitofp_2i16_to_2f64(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_2i16_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_2i16_to_2f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[X86][SSE] Sign extension for target vector sizes less than 128 bits (pt2) Add support for v2i8/v2i16 to v2f64 by using a sign extension to v2i32 before conversion to v2f64. Differential Revision: http://reviews.llvm.org/D10589 llvm-svn: 241325
2015-07-03 16:01:36 +08:00
; AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: retq
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) {
; SSE-LABEL: sitofp_8i16_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_8i16_to_2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_8i16_to_2f64:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_8i16_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @sitofp_2i8_to_2f64(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_2i8_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_2i8_to_2f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[X86][SSE] Sign extension for target vector sizes less than 128 bits (pt2) Add support for v2i8/v2i16 to v2f64 by using a sign extension to v2i32 before conversion to v2f64. Differential Revision: http://reviews.llvm.org/D10589 llvm-svn: 241325
2015-07-03 16:01:36 +08:00
; AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: retq
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) {
; SSE-LABEL: sitofp_16i8_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_16i8_to_2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_16i8_to_2f64:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_16i8_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <16 x i8> %a to <16 x double>
%shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @sitofp_4i64_to_4f64(<4 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i64_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: cvtsi2sdq %rax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2sdq %rax, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: movapd %xmm3, %xmm1
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: sitofp_4i64_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: sitofp_4i64_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_4i64_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_4i64_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_4i64_to_4f64:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_4i64_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2pd %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @sitofp_4i32_to_4f64(<4 x i32> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i32_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_4i32_to_4f64:
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
%cvt = sitofp <4 x i32> %a to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @sitofp_4i16_to_4f64(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_4i16_to_4f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[X86][SSE] Improved support for vector i16 to float conversions. Added explicit sign extension for v4i16/v8i16 to v4i32/v8i32 before conversion to floats. Matches existing support for v4i8/v8i8. Follow up to D10433 llvm-svn: 239966
2015-06-18 06:43:34 +08:00
; AVX-NEXT: vpmovsxwd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i16> %shuf to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x double> @sitofp_8i16_to_4f64(<8 x i16> %a) {
; SSE-LABEL: sitofp_8i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_8i16_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_8i16_to_4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_8i16_to_4f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @sitofp_4i8_to_4f64(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_4i8_to_4f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
; AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x double> @sitofp_16i8_to_4f64(<16 x i8> %a) {
; SSE-LABEL: sitofp_16i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_16i8_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_16i8_to_4f64:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_16i8_to_4f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <16 x i8> %a to <16 x double>
%shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
; Unsigned Integer to Double
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_2i64_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm3, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE-NEXT: subpd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_2i64_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; VEX-NEXT: vsubpd %xmm3, %xmm2, %xmm2
; VEX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vsubpd %xmm3, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; VEX-NEXT: vhaddpd %xmm0, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: retq
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512F-LABEL: uitofp_2i64_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_2i64_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: uitofp_2i64_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vpextrq $1, %xmm0, %rax
; AVX512DQ-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512DQ-NEXT: vmovq %xmm0, %rax
; AVX512DQ-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512DQ-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_2i64_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = uitofp <2 x i64> %a to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_2i32_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm3, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE-NEXT: subpd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_2i32_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; VEX-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; VEX-NEXT: vsubpd %xmm3, %xmm2, %xmm2
; VEX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vsubpd %xmm3, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; VEX-NEXT: vhaddpd %xmm0, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_2i32_to_2f64:
; AVX512F: # BB#0:
[X86][AVX512F] Add support for uint_to_fp v2i32 to v2f64 on AVX512F-only targets Use 512-bit instructions (we already do something similar for uint_to_fp v4i32 to v4f64) llvm-svn: 287491
2016-11-20 22:03:23 +08:00
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_2i32_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_2i32_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_2i32_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
%cvt = uitofp <2 x i32> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) {
; SSE-LABEL: uitofp_4i32_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm3, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE-NEXT: subpd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_4i32_to_2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vcvtdq2pd %xmm1, %ymm1
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_4i32_to_2f64:
; AVX2: # BB#0:
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vcvtdq2pd %xmm1, %ymm1
; AVX2-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2
; AVX2-NEXT: vmulpd %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_4i32_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i32_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2pd %xmm0, %ymm0
; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_4i32_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i32_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %ymm0
; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <4 x i32> %a to <4 x double>
%shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @uitofp_2i16_to_2f64(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_2i16_to_2f64:
; SSE: # BB#0:
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: uitofp_2i16_to_2f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
[X86][SSE] Improved i8/i16 to f64 uint2fp vector conversions Followup to D10433 and D10589 that fixes i8/i16 uint2fp vector conversions by zero extending to i32 and using the sint2fp path (unless the target does actually support uint2fp). llvm-svn: 241394
2015-07-04 23:33:34 +08:00
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: retq
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%cvt = uitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @uitofp_8i16_to_2f64(<8 x i16> %a) {
; SSE-LABEL: uitofp_8i16_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_8i16_to_2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_8i16_to_2f64:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_8i16_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <2 x double> @uitofp_2i8_to_2f64(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_2i8_to_2f64:
; SSE: # BB#0:
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: uitofp_2i8_to_2f64:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
[X86][SSE] Improved i8/i16 to f64 uint2fp vector conversions Followup to D10433 and D10589 that fixes i8/i16 uint2fp vector conversions by zero extending to i32 and using the sint2fp path (unless the target does actually support uint2fp). llvm-svn: 241394
2015-07-04 23:33:34 +08:00
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: retq
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%cvt = uitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <2 x double> @uitofp_16i8_to_2f64(<16 x i8> %a) {
; SSE-LABEL: uitofp_16i8_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_16i8_to_2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_16i8_to_2f64:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_16i8_to_2f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <16 x i8> %a to <16 x double>
%shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i64_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: movapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm4, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[2,3,0,1]
; SSE-NEXT: addpd %xmm5, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE-NEXT: subpd %xmm4, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm5
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm5[0]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: subpd %xmm4, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,0,1]
; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE-NEXT: subpd %xmm4, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: uitofp_4i64_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX1-NEXT: vmovapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; AVX1-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm1, %xmm1
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX1-NEXT: vhaddpd %xmm1, %xmm3, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX1-NEXT: vhaddpd %xmm0, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: uitofp_4i64_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX2-NEXT: vmovapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; AVX2-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm1, %xmm1
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX2-NEXT: vhaddpd %xmm1, %xmm3, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX2-NEXT: vhaddpd %xmm0, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_4i64_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i64_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_4i64_to_4f64:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i64_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2pd %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = uitofp <4 x i64> %a to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @uitofp_4i32_to_4f64(<4 x i32> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i32_to_4f64:
; SSE: # BB#0:
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm2
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [1127219200,1160773632,0,0]
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: movapd {{.*#+}} xmm5 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm5, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,0,1]
; SSE-NEXT: addpd %xmm6, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; SSE-NEXT: subpd %xmm5, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm6
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm6[0]
; SSE-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[2,3,0,1]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: subpd %xmm5, %xmm2
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; SSE-NEXT: subpd %xmm5, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm2
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: uitofp_4i32_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vcvtdq2pd %xmm1, %ymm1
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: uitofp_4i32_to_4f64:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vcvtdq2pd %xmm1, %ymm1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX2-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vmulpd %ymm2, %ymm1, %ymm1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_4i32_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i32_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2pd %xmm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_4i32_to_4f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i32_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %ymm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = uitofp <4 x i32> %a to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @uitofp_4i16_to_4f64(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_4i16_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i16> %shuf to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x double> @uitofp_8i16_to_4f64(<8 x i16> %a) {
; SSE-LABEL: uitofp_8i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_8i16_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_8i16_to_4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_8i16_to_4f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x double> @uitofp_4i8_to_4f64(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_4i8_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i8> %shuf to <4 x double>
ret <4 x double> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x double> @uitofp_16i8_to_4f64(<16 x i8> %a) {
; SSE-LABEL: uitofp_16i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_16i8_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_16i8_to_4f64:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_16i8_to_4f64:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <16 x i8> %a to <16 x double>
%shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
; Signed Integer to Float
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @sitofp_2i64_to_4f32(<2 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_2i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; VEX-LABEL: sitofp_2i64_to_4f32:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: retq
;
; AVX512F-LABEL: sitofp_2i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_2i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: sitofp_2i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_2i64_to_4f32:
; AVX512VLDQ: # BB#0:
[X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering llvm-svn: 287877
2016-11-24 21:38:59 +08:00
; AVX512VLDQ-NEXT: vcvtqq2ps %xmm0, %xmm0
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = sitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %ext
}
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
define <4 x float> @sitofp_2i64_to_4f32_zero(<2 x i64> %a) {
; SSE-LABEL: sitofp_2i64_to_4f32_zero:
; SSE: # BB#0:
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-NEXT: retq
;
; VEX-LABEL: sitofp_2i64_to_4f32_zero:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
; VEX-NEXT: retq
;
; AVX512F-LABEL: sitofp_2i64_to_4f32_zero:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_2i64_to_4f32_zero:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: sitofp_2i64_to_4f32_zero:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_2i64_to_4f32_zero:
; AVX512VLDQ: # BB#0:
[X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering llvm-svn: 287877
2016-11-24 21:38:59 +08:00
; AVX512VLDQ-NEXT: vcvtqq2ps %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX512VLDQ-NEXT: retq
%cvt = sitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %ext
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @sitofp_4i64_to_4f32_undef(<2 x i64> %a) {
; SSE-LABEL: sitofp_4i64_to_4f32_undef:
; SSE: # BB#0:
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; VEX-LABEL: sitofp_4i64_to_4f32_undef:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: retq
;
; AVX512F-LABEL: sitofp_4i64_to_4f32_undef:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_4i64_to_4f32_undef:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: sitofp_4i64_to_4f32_undef:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_4i64_to_4f32_undef:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%cvt = sitofp <4 x i64> %ext to <4 x float>
ret <4 x float> %cvt
}
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
define <4 x float> @sitofp_4i32_to_4f32(<4 x i32> %a) {
; SSE-LABEL: sitofp_4i32_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_4i32_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
%cvt = sitofp <4 x i32> %a to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @sitofp_4i16_to_4f32(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_4i16_to_4f32:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
[X86][SSE] Improved support for vector i16 to float conversions. Added explicit sign extension for v4i16/v8i16 to v4i32/v8i32 before conversion to floats. Matches existing support for v4i8/v8i8. Follow up to D10433 llvm-svn: 239966
2015-06-18 06:43:34 +08:00
; AVX-NEXT: vpmovsxwd %xmm0, %xmm0
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i16> %shuf to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @sitofp_8i16_to_4f32(<8 x i16> %a) {
; SSE-LABEL: sitofp_8i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_8i16_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_8i16_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_8i16_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <8 x i16> %a to <8 x float>
%shuf = shufflevector <8 x float> %cvt, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @sitofp_4i8_to_4f32(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX-LABEL: sitofp_4i8_to_4f32:
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
; AVX: # BB#0:
; AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i8> %shuf to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @sitofp_16i8_to_4f32(<16 x i8> %a) {
; SSE-LABEL: sitofp_16i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_16i8_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_16i8_to_4f32:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_16i8_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <16 x i8> %a to <16 x float>
%shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @sitofp_4i64_to_4f32(<4 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_4i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: sitofp_4i64_to_4f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: sitofp_4i64_to_4f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_4i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_4i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_4i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_4i64_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %cvt
}
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
define <8 x float> @sitofp_8i32_to_8f32(<8 x i32> %a) {
; SSE-LABEL: sitofp_8i32_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_8i32_to_8f32:
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX-NEXT: retq
%cvt = sitofp <8 x i32> %a to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <8 x float> @sitofp_8i16_to_8f32(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_8i16_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm2
[X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
2015-11-14 03:47:43 +08:00
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: sitofp_8i16_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: sitofp_8i16_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_8i16_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%cvt = sitofp <8 x i16> %a to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <8 x float> @sitofp_8i8_to_8f32(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: sitofp_8i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: sitofp_8i8_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: sitofp_8i8_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
[X86][AVX2] Fix SIGN_EXTEND vector handling on AVX2 targets. On AVX2 target we are poorly legalizing SIGN_EXTEND ops for which the input's legalized type doesn't have the same number of elements as the destination, resulting in an ANY_EXTEND followed by a SIGN_EXTEND_INREG. This patch uses the existing SIGN_EXTEND -> SIGN_EXTEND_VECTOR_INREG combine to extend the input to the size of the result and using SIGN_EXTEND_VECTOR_INREG instead. Differential Revision: http://reviews.llvm.org/D16994 llvm-svn: 260210
2016-02-09 16:19:19 +08:00
; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_8i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd %xmm0, %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%cvt = sitofp <8 x i8> %shuf to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <8 x float> @sitofp_16i8_to_8f32(<16 x i8> %a) {
; SSE-LABEL: sitofp_16i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_16i8_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_16i8_to_8f32:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_16i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = sitofp <16 x i8> %a to <16 x float>
%shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x float> %shuf
}
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
; Unsigned Integer to Float
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_2i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB39_1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#2:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB39_3
; SSE-NEXT: .LBB39_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: xorps %xmm0, %xmm0
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB39_3:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB39_4
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#5:
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB39_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm1, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_2i64_to_4f32:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB39_1
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: jmp .LBB39_3
; VEX-NEXT: .LBB39_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB39_3:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB39_4
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: jmp .LBB39_6
; VEX-NEXT: .LBB39_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB39_6:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; VEX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB39_8
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#7:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB39_8:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: retq
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512F-LABEL: uitofp_2i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_2i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: uitofp_2i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_2i64_to_4f32:
; AVX512VLDQ: # BB#0:
[X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering llvm-svn: 287877
2016-11-24 21:38:59 +08:00
; AVX512VLDQ-NEXT: vcvtuqq2ps %xmm0, %xmm0
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = uitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %ext
}
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) {
; SSE-LABEL: uitofp_2i64_to_2f32:
; SSE: # BB#0:
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
; SSE-NEXT: js .LBB40_1
; SSE-NEXT: # BB#2:
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: jmp .LBB40_3
; SSE-NEXT: .LBB40_1:
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: addss %xmm1, %xmm1
; SSE-NEXT: .LBB40_3:
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: testq %rax, %rax
; SSE-NEXT: js .LBB40_4
; SSE-NEXT: # BB#5:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: jmp .LBB40_6
; SSE-NEXT: .LBB40_4:
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: addss %xmm0, %xmm0
; SSE-NEXT: .LBB40_6:
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-NEXT: retq
;
; VEX-LABEL: uitofp_2i64_to_2f32:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
; VEX-NEXT: js .LBB40_1
; VEX-NEXT: # BB#2:
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; VEX-NEXT: jmp .LBB40_3
; VEX-NEXT: .LBB40_1:
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1
; VEX-NEXT: .LBB40_3:
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
; VEX-NEXT: js .LBB40_4
; VEX-NEXT: # BB#5:
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
; VEX-NEXT: retq
; VEX-NEXT: .LBB40_4:
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
; VEX-NEXT: retq
;
; AVX512F-LABEL: uitofp_2i64_to_2f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_2i64_to_2f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: uitofp_2i64_to_2f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_2i64_to_2f32:
; AVX512VLDQ: # BB#0:
[X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering llvm-svn: 287877
2016-11-24 21:38:59 +08:00
; AVX512VLDQ-NEXT: vcvtuqq2ps %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX512VLDQ-NEXT: retq
%cvt = uitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %ext
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) {
; SSE-LABEL: uitofp_4i64_to_4f32_undef:
; SSE: # BB#0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: testq %rax, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB41_2
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: # BB#1:
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB41_2:
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB41_3
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: # BB#4:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB41_5
; SSE-NEXT: .LBB41_3:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: xorps %xmm0, %xmm0
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: addss %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB41_5:
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB41_6
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: # BB#7:
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB41_8
; SSE-NEXT: .LBB41_6:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: addss %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB41_8:
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_4i64_to_4f32_undef:
; VEX: # BB#0:
; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB41_1
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: jmp .LBB41_3
; VEX-NEXT: .LBB41_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB41_3:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB41_4
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: jmp .LBB41_6
; VEX-NEXT: .LBB41_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; VEX-NEXT: movq %rax, %rcx
; VEX-NEXT: shrq %rcx
; VEX-NEXT: andl $1, %eax
; VEX-NEXT: orq %rcx, %rax
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB41_6:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; VEX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; VEX-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: js .LBB41_8
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: # BB#7:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; VEX-NEXT: .LBB41_8:
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: retq
;
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512F-LABEL: uitofp_4i64_to_4f32_undef:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i64_to_4f32_undef:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq
;
; AVX512DQ-LABEL: uitofp_4i64_to_4f32_undef:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i64_to_4f32_undef:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
; AVX512VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%cvt = uitofp <4 x i64> %ext to <4 x float>
ret <4 x float> %cvt
}
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) {
; SSE-LABEL: uitofp_4i32_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: por {{.*}}(%rip), %xmm1
; SSE-NEXT: psrld $16, %xmm0
; SSE-NEXT: por {{.*}}(%rip), %xmm0
; SSE-NEXT: addps {{.*}}(%rip), %xmm0
; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_4i32_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_4i32_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm2
; AVX2-NEXT: vaddps %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_4i32_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i32_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_4i32_to_4f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i32_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2ps %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
%cvt = uitofp <4 x i32> %a to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @uitofp_4i16_to_4f32(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_4i16_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i16> %shuf to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) {
; SSE-LABEL: uitofp_8i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_8i16_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_8i16_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_8i16_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <8 x i16> %a to <8 x float>
%shuf = shufflevector <8 x float> %cvt, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @uitofp_4i8_to_4f32(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_4i8_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = uitofp <4 x i8> %shuf to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) {
; SSE-LABEL: uitofp_16i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_16i8_to_4f32:
; AVX1: # BB#0:
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_16i8_to_4f32:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_16i8_to_4f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <16 x i8> %a to <16 x float>
%shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %shuf
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_4i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB47_1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#2:
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB47_3
; SSE-NEXT: .LBB47_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB47_3:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB47_4
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#5:
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB47_6
; SSE-NEXT: .LBB47_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB47_6:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB47_7
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#8:
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB47_9
; SSE-NEXT: .LBB47_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB47_9:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: movd %xmm0, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB47_10
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: # BB#11:
; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB47_12
; SSE-NEXT: .LBB47_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: xorps %xmm0, %xmm0
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: addss %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB47_12:
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: uitofp_4i64_to_4f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB47_1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB47_3
; AVX1-NEXT: .LBB47_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB47_3:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB47_4
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB47_6
; AVX1-NEXT: .LBB47_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB47_6:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB47_7
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB47_9
; AVX1-NEXT: .LBB47_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB47_9:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB47_10
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB47_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: uitofp_4i64_to_4f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB47_1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB47_3
; AVX2-NEXT: .LBB47_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB47_3:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB47_4
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB47_6
; AVX2-NEXT: .LBB47_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB47_6:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB47_7
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB47_9
; AVX2-NEXT: .LBB47_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB47_9:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB47_10
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB47_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_4i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_4i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_4i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_4i64_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0
; AVX512VLDQ-NEXT: retq
[SSE] Added vector int (i32 and i64) -> float/double conversion tests llvm-svn: 236385
2015-05-02 19:42:47 +08:00
%cvt = uitofp <4 x i64> %a to <4 x float>
ret <4 x float> %cvt
}
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
define <8 x float> @uitofp_8i32_to_8f32(<8 x i32> %a) {
; SSE-LABEL: uitofp_8i32_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [1258291200,1258291200,1258291200,1258291200]
; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: psrld $16, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm5 = [1392508928,1392508928,1392508928,1392508928]
; SSE-NEXT: por %xmm5, %xmm0
; SSE-NEXT: movaps {{.*#+}} xmm6 = [-5.497642e+11,-5.497642e+11,-5.497642e+11,-5.497642e+11]
; SSE-NEXT: addps %xmm6, %xmm0
; SSE-NEXT: addps %xmm3, %xmm0
; SSE-NEXT: pand %xmm1, %xmm2
; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: psrld $16, %xmm1
; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: addps %xmm6, %xmm1
; SSE-NEXT: addps %xmm2, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_8i32_to_8f32:
; AVX1: # BB#0:
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_8i32_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15]
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
; AVX2-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_8i32_to_8f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_8i32_to_8f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2ps %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_8i32_to_8f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_8i32_to_8f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2ps %ymm0, %ymm0
; AVX512VLDQ-NEXT: retq
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
%cvt = uitofp <8 x i32> %a to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <8 x float> @uitofp_8i16_to_8f32(<8 x i16> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_8i16_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm2, %xmm2
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: uitofp_8i16_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: uitofp_8i16_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_8i16_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%cvt = uitofp <8 x i16> %a to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define <8 x float> @uitofp_8i8_to_8f32(<16 x i8> %a) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: uitofp_8i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
[X86][SSE] Match zero/any extension shuffles that don't start from the first element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
2015-09-22 16:16:08 +08:00
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm2, %xmm2
[X86][SSE] Match zero/any extension shuffles that don't start from the first element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
2015-09-22 16:16:08 +08:00
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: uitofp_8i8_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1: # BB#0:
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
[DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
2015-08-01 18:01:46 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: uitofp_8i8_to_8f32:
[X86][AVX2] Added AVX2 SINT_TO_FP/UINT_TO_FP tests llvm-svn: 240013
2015-06-18 20:32:28 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_8i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: retq
[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions llvm-svn: 239767
2015-06-16 05:49:31 +08:00
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%cvt = uitofp <8 x i8> %shuf to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
define <8 x float> @uitofp_16i8_to_8f32(<16 x i8> %a) {
; SSE-LABEL: uitofp_16i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: pxor %xmm1, %xmm1
[X86][SSE] Match zero/any extension shuffles that don't start from the first element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
2015-09-22 16:16:08 +08:00
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm2, %xmm2
[X86][SSE] Match zero/any extension shuffles that don't start from the first element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
2015-09-22 16:16:08 +08:00
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; SSE-NEXT: cvtdq2ps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_16i8_to_8f32:
; AVX1: # BB#0:
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_16i8_to_8f32:
; AVX2: # BB#0:
[X86][AVX2] Improve sign/zero extension on AVX2 targets Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
2016-08-07 05:21:12 +08:00
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_16i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512-NEXT: retq
[X86][SSE] Added additional fp/int tests. Demonstrates some shortfalls in subvector(cvt(x)) compared to cvt(subvector(x)) patterns - especially on AVX/AVX2 targets. llvm-svn: 242614
2015-07-19 01:05:39 +08:00
%cvt = uitofp <16 x i8> %a to <16 x float>
%shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x float> %shuf
}
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
;
; Load Signed Integer to Double
;
define <2 x double> @sitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; SSE-LABEL: sitofp_load_2i64_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2sdq %rax, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: sitofp_load_2i64_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vmovdqa (%rdi), %xmm0
; VEX-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; VEX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_load_2i64_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_load_2i64_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %xmm0
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_load_2i64_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm0
; AVX512DQ-NEXT: vpextrq $1, %xmm0, %rax
; AVX512DQ-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX512DQ-NEXT: vmovq %xmm0, %rax
; AVX512DQ-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX512DQ-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_load_2i64_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2pd (%rdi), %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i64>, <2 x i64> *%a
%cvt = sitofp <2 x i64> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @sitofp_load_2i32_to_2f64(<2 x i32> *%a) {
; SSE-LABEL: sitofp_load_2i32_to_2f64:
; SSE: # BB#0:
[X86][SSE] Add load-folding patterns for (V)CVTDQ2PD (PR27291) Added patterns for (V)CVTDQ2PD -> 2f64 loading from a 64-bit source. llvm-svn: 271269
2016-05-31 20:04:35 +08:00
; SSE-NEXT: cvtdq2pd (%rdi), %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: sitofp_load_2i32_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vcvtdq2pd (%rdi), %xmm0
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_load_2i32_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vcvtdq2pd (%rdi), %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_load_2i32_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VL-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_load_2i32_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vcvtdq2pd (%rdi), %xmm0
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_load_2i32_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX512VLDQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VLDQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i32>, <2 x i32> *%a
%cvt = sitofp <2 x i32> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @sitofp_load_2i16_to_2f64(<2 x i16> *%a) {
; SSE-LABEL: sitofp_load_2i16_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_2i16_to_2f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX-NEXT: retq
%ld = load <2 x i16>, <2 x i16> *%a
%cvt = sitofp <2 x i16> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @sitofp_load_2i8_to_2f64(<2 x i8> *%a) {
; SSE-LABEL: sitofp_load_2i8_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movzwl (%rdi), %eax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_2i8_to_2f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX-NEXT: retq
%ld = load <2 x i8>, <2 x i8> *%a
%cvt = sitofp <2 x i8> %ld to <2 x double>
ret <2 x double> %cvt
}
define <4 x double> @sitofp_load_4i64_to_4f64(<4 x i64> *%a) {
; SSE-LABEL: sitofp_load_4i64_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm2
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2sdq %rax, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2sdq %rax, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2sdq %rax, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_load_4i64_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovaps (%rdi), %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_load_4i64_to_4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_load_4i64_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_load_4i64_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_load_4i64_to_4f64:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_load_4i64_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2pd (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i64>, <4 x i64> *%a
%cvt = sitofp <4 x i64> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @sitofp_load_4i32_to_4f64(<4 x i32> *%a) {
; SSE-LABEL: sitofp_load_4i32_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i32_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2pd (%rdi), %ymm0
; AVX-NEXT: retq
%ld = load <4 x i32>, <4 x i32> *%a
%cvt = sitofp <4 x i32> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @sitofp_load_4i16_to_4f64(<4 x i16> *%a) {
; SSE-LABEL: sitofp_load_4i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i16_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
%ld = load <4 x i16>, <4 x i16> *%a
%cvt = sitofp <4 x i16> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @sitofp_load_4i8_to_4f64(<4 x i8> *%a) {
; SSE-LABEL: sitofp_load_4i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i8_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
%ld = load <4 x i8>, <4 x i8> *%a
%cvt = sitofp <4 x i8> %ld to <4 x double>
ret <4 x double> %cvt
}
;
; Load Unsigned Integer to Double
;
define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; SSE-LABEL: uitofp_load_2i64_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: movapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm4, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE-NEXT: subpd %xmm4, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_load_2i64_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vmovdqa (%rdi), %xmm0
; VEX-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; VEX-NEXT: vsubpd %xmm3, %xmm2, %xmm2
; VEX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vsubpd %xmm3, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; VEX-NEXT: vhaddpd %xmm0, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_2i64_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_2i64_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %xmm0
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_2i64_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm0
; AVX512DQ-NEXT: vpextrq $1, %xmm0, %rax
; AVX512DQ-NEXT: vcvtusi2sdq %rax, %xmm1, %xmm1
; AVX512DQ-NEXT: vmovq %xmm0, %rax
; AVX512DQ-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm0
; AVX512DQ-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_2i64_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2pd (%rdi), %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i64>, <2 x i64> *%a
%cvt = uitofp <2 x i64> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @uitofp_load_2i32_to_2f64(<2 x i32> *%a) {
; SSE-LABEL: uitofp_load_2i32_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: movapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm4, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE-NEXT: subpd %xmm4, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_load_2i32_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; VEX-NEXT: vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
; VEX-NEXT: vsubpd %xmm3, %xmm2, %xmm2
; VEX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; VEX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; VEX-NEXT: vsubpd %xmm3, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; VEX-NEXT: vhaddpd %xmm0, %xmm2, %xmm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_2i32_to_2f64:
; AVX512F: # BB#0:
[X86][AVX512F] Add support for uint_to_fp v2i32 to v2f64 on AVX512F-only targets Use 512-bit instructions (we already do something similar for uint_to_fp v4i32 to v4f64) llvm-svn: 287491
2016-11-20 22:03:23 +08:00
; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_2i32_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_2i32_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_2i32_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
; AVX512VLDQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i32>, <2 x i32> *%a
%cvt = uitofp <2 x i32> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @uitofp_load_2i16_to_2f64(<2 x i16> *%a) {
; SSE-LABEL: uitofp_load_2i16_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_load_2i16_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; VEX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_2i16_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_2i16_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VL-NEXT: vpxord %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
; AVX512VL-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_2i16_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_2i16_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
; AVX512VLDQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VLDQ-NEXT: vpxord %xmm1, %xmm1, %xmm1
; AVX512VLDQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
; AVX512VLDQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i16>, <2 x i16> *%a
%cvt = uitofp <2 x i16> %ld to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @uitofp_load_2i8_to_2f64(<2 x i8> *%a) {
; SSE-LABEL: uitofp_load_2i8_to_2f64:
; SSE: # BB#0:
; SSE-NEXT: movzwl (%rdi), %eax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-NEXT: retq
;
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; VEX-LABEL: uitofp_load_2i8_to_2f64:
; VEX: # BB#0:
; VEX-NEXT: movzwl (%rdi), %eax
; VEX-NEXT: vmovd %eax, %xmm0
; VEX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
; VEX-NEXT: retq
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_2i8_to_2f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: movzwl (%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm0
; AVX512F-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_2i8_to_2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[u],zero,zero,zero,xmm0[u],zero,zero,zero
; AVX512VL-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_2i8_to_2f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: movzwl (%rdi), %eax
; AVX512DQ-NEXT: vmovd %eax, %xmm0
; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_2i8_to_2f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
; AVX512VLDQ-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[u],zero,zero,zero,xmm0[u],zero,zero,zero
; AVX512VLDQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <2 x i8>, <2 x i8> *%a
%cvt = uitofp <2 x i8> %ld to <2 x double>
ret <2 x double> %cvt
}
define <4 x double> @uitofp_load_4i64_to_4f64(<4 x i64> *%a) {
; SSE-LABEL: uitofp_load_4i64_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; SSE-NEXT: movapd {{.*#+}} xmm5 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm5, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; SSE-NEXT: subpd %xmm5, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm4[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE-NEXT: subpd %xmm5, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; SSE-NEXT: subpd %xmm5, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,0,1]
; SSE-NEXT: addpd %xmm4, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i64_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovaps (%rdi), %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX1-NEXT: vmovapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; AVX1-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm1, %xmm1
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX1-NEXT: vhaddpd %xmm1, %xmm3, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX1-NEXT: vsubpd %xmm4, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX1-NEXT: vhaddpd %xmm0, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_4i64_to_4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX2-NEXT: vmovapd {{.*#+}} xmm4 = [4.503600e+15,1.934281e+25]
; AVX2-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm1, %xmm1
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX2-NEXT: vhaddpd %xmm1, %xmm3, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX2-NEXT: vsubpd %xmm4, %xmm0, %xmm0
[X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. This occurs during UINT_TO_FP v2f64 lowering. We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle llvm-svn: 287676
2016-11-23 01:50:06 +08:00
; AVX2-NEXT: vhaddpd %xmm0, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_4i64_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_4i64_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2sdq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_4i64_to_4f64:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_4i64_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2pd (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i64>, <4 x i64> *%a
%cvt = uitofp <4 x i64> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @uitofp_load_4i32_to_4f64(<4 x i32> *%a) {
; SSE-LABEL: uitofp_load_4i32_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm2
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [1127219200,1160773632,0,0]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
; SSE-NEXT: movapd {{.*#+}} xmm6 = [4.503600e+15,1.934281e+25]
; SSE-NEXT: subpd %xmm6, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm0
; SSE-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
; SSE-NEXT: subpd %xmm6, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[2,3,0,1]
; SSE-NEXT: addpd %xmm5, %xmm3
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; SSE-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1]
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; SSE-NEXT: subpd %xmm6, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
; SSE-NEXT: addpd %xmm2, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
; SSE-NEXT: subpd %xmm6, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,0,1]
; SSE-NEXT: addpd %xmm3, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i32_to_4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vcvtdq2pd %xmm1, %ymm1
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_4i32_to_4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vcvtdq2pd %xmm1, %ymm1
; AVX2-NEXT: vbroadcastsd {{.*}}(%rip), %ymm2
; AVX2-NEXT: vmulpd %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_4i32_to_4f64:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_4i32_to_4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2pd (%rdi), %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_4i32_to_4f64:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_4i32_to_4f64:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2pd (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i32>, <4 x i32> *%a
%cvt = uitofp <4 x i32> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @uitofp_load_4i16_to_4f64(<4 x i16> *%a) {
; SSE-LABEL: uitofp_load_4i16_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_load_4i16_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i16>, <4 x i16> *%a
%cvt = uitofp <4 x i16> %ld to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @uitofp_load_4i8_to_4f64(<4 x i8> *%a) {
; SSE-LABEL: uitofp_load_4i8_to_4f64:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE-NEXT: retq
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_load_4i8_to_4f64:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i8>, <4 x i8> *%a
%cvt = uitofp <4 x i8> %ld to <4 x double>
ret <4 x double> %cvt
}
;
; Load Signed Integer to Float
;
define <4 x float> @sitofp_load_4i64_to_4f32(<4 x i64> *%a) {
; SSE-LABEL: sitofp_load_4i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm2
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_load_4i64_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_load_4i64_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_load_4i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_load_4i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_load_4i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_load_4i64_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2psy (%rdi), %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i64>, <4 x i64> *%a
%cvt = sitofp <4 x i64> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @sitofp_load_4i32_to_4f32(<4 x i32> *%a) {
; SSE-LABEL: sitofp_load_4i32_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2ps (%rdi), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i32_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2ps (%rdi), %xmm0
; AVX-NEXT: retq
%ld = load <4 x i32>, <4 x i32> *%a
%cvt = sitofp <4 x i32> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @sitofp_load_4i16_to_4f32(<4 x i16> *%a) {
; SSE-LABEL: sitofp_load_4i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i16_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
%ld = load <4 x i16>, <4 x i16> *%a
%cvt = sitofp <4 x i16> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @sitofp_load_4i8_to_4f32(<4 x i8> *%a) {
; SSE-LABEL: sitofp_load_4i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_4i8_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
%ld = load <4 x i8>, <4 x i8> *%a
%cvt = sitofp <4 x i8> %ld to <4 x float>
ret <4 x float> %cvt
}
define <8 x float> @sitofp_load_8i64_to_8f32(<8 x i64> *%a) {
; SSE-LABEL: sitofp_load_8i64_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm2
; SSE-NEXT: movdqa 32(%rdi), %xmm3
; SSE-NEXT: movdqa 48(%rdi), %xmm4
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm5
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movd %xmm4, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,0,1]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_load_8i64_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_load_8i64_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vmovq %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: sitofp_load_8i64_to_8f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; AVX512F-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; AVX512F-NEXT: vmovq %xmm2, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm2, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX512F-NEXT: vextracti32x4 $1, %zmm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: sitofp_load_8i64_to_8f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; AVX512VL-NEXT: vmovq %xmm2, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %zmm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: sitofp_load_8i64_to_8f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vcvtqq2ps (%rdi), %ymm0
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: sitofp_load_8i64_to_8f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtqq2ps (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i64>, <8 x i64> *%a
%cvt = sitofp <8 x i64> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @sitofp_load_8i32_to_8f32(<8 x i32> *%a) {
; SSE-LABEL: sitofp_load_8i32_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: cvtdq2ps (%rdi), %xmm0
; SSE-NEXT: cvtdq2ps 16(%rdi), %xmm1
; SSE-NEXT: retq
;
; AVX-LABEL: sitofp_load_8i32_to_8f32:
; AVX: # BB#0:
; AVX-NEXT: vcvtdq2ps (%rdi), %ymm0
; AVX-NEXT: retq
%ld = load <8 x i32>, <8 x i32> *%a
%cvt = sitofp <8 x i32> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @sitofp_load_8i16_to_8f32(<8 x i16> *%a) {
; SSE-LABEL: sitofp_load_8i16_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_load_8i16_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
; AVX1-NEXT: vpmovsxwd 8(%rdi), %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_load_8i16_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd (%rdi), %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_load_8i16_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxwd (%rdi), %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i16>, <8 x i16> *%a
%cvt = sitofp <8 x i16> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @sitofp_load_8i8_to_8f32(<8 x i8> *%a) {
; SSE-LABEL: sitofp_load_8i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
; SSE-NEXT: psrad $24, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: sitofp_load_8i8_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovsxbw (%rdi), %xmm0
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: sitofp_load_8i8_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxbd (%rdi), %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: sitofp_load_8i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovsxbd (%rdi), %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i8>, <8 x i8> *%a
%cvt = sitofp <8 x i8> %ld to <8 x float>
ret <8 x float> %cvt
}
;
; Load Unsigned Integer to Float
;
define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) {
; SSE-LABEL: uitofp_load_4i64_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm3
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB76_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#2:
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB76_3
; SSE-NEXT: .LBB76_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB76_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB76_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#5:
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB76_6
; SSE-NEXT: .LBB76_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB76_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB76_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#8:
; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB76_9
; SSE-NEXT: .LBB76_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: xorps %xmm3, %xmm3
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB76_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB76_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#11:
; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB76_12
; SSE-NEXT: .LBB76_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB76_12:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i64_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB76_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB76_3
; AVX1-NEXT: .LBB76_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB76_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB76_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB76_6
; AVX1-NEXT: .LBB76_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB76_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB76_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB76_9
; AVX1-NEXT: .LBB76_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB76_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB76_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB76_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_4i64_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB76_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB76_3
; AVX2-NEXT: .LBB76_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB76_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB76_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB76_6
; AVX2-NEXT: .LBB76_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB76_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB76_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB76_9
; AVX2-NEXT: .LBB76_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB76_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB76_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB76_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_4i64_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_4i64_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %ymm0
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_4i64_to_4f32:
; AVX512DQ: # BB#0:
[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287762
2016-11-23 22:01:18 +08:00
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_4i64_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2psy (%rdi), %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i64>, <4 x i64> *%a
%cvt = uitofp <4 x i64> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) {
; SSE-LABEL: uitofp_load_4i32_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: por {{.*}}(%rip), %xmm1
; SSE-NEXT: psrld $16, %xmm0
; SSE-NEXT: por {{.*}}(%rip), %xmm0
; SSE-NEXT: addps {{.*}}(%rip), %xmm0
; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i32_to_4f32:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_4i32_to_4f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %xmm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm2
; AVX2-NEXT: vaddps %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_4i32_to_4f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_4i32_to_4f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2ps (%rdi), %xmm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_4i32_to_4f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_4i32_to_4f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2ps (%rdi), %xmm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i32>, <4 x i32> *%a
%cvt = uitofp <4 x i32> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @uitofp_load_4i16_to_4f32(<4 x i16> *%a) {
; SSE-LABEL: uitofp_load_4i16_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_load_4i16_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i16>, <4 x i16> *%a
%cvt = uitofp <4 x i16> %ld to <4 x float>
ret <4 x float> %cvt
}
define <4 x float> @uitofp_load_4i8_to_4f32(<4 x i8> *%a) {
; SSE-LABEL: uitofp_load_4i8_to_4f32:
; SSE: # BB#0:
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: retq
;
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX-LABEL: uitofp_load_4i8_to_4f32:
; AVX: # BB#0:
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <4 x i8>, <4 x i8> *%a
%cvt = uitofp <4 x i8> %ld to <4 x float>
ret <4 x float> %cvt
}
define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) {
; SSE-LABEL: uitofp_load_8i64_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: movdqa 16(%rdi), %xmm5
; SSE-NEXT: movdqa 32(%rdi), %xmm2
; SSE-NEXT: movdqa 48(%rdi), %xmm3
; SSE-NEXT: movd %xmm5, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#2:
; SSE-NEXT: cvtsi2ssq %rax, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_3
; SSE-NEXT: .LBB80_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm4, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#5:
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_6
; SSE-NEXT: .LBB80_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm0, %xmm0
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,0,1]
; SSE-NEXT: movd %xmm5, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#8:
; SSE-NEXT: cvtsi2ssq %rax, %xmm6
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_9
; SSE-NEXT: .LBB80_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm6
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm6, %xmm6
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE-NEXT: movd %xmm1, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#11:
; SSE-NEXT: xorps %xmm5, %xmm5
; SSE-NEXT: cvtsi2ssq %rax, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_12
; SSE-NEXT: .LBB80_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Relax the clearance calculating for breaking partial register dependency. Summary: LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency. Reviewers: wmi, davidxl, stoklund, zansari, myatsina, RKSimon, DavidKreitzer, mkuper, joerg, spatel Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21560 llvm-svn: 274068
2016-06-29 05:19:34 +08:00
; SSE-NEXT: xorps %xmm5, %xmm5
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm5
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm5, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_12:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_13
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#14:
; SSE-NEXT: cvtsi2ssq %rax, %xmm7
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_15
; SSE-NEXT: .LBB80_13:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
; SSE-NEXT: cvtsi2ssq %rax, %xmm7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm7, %xmm7
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_15:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_16
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#17:
Relax the clearance calculating for breaking partial register dependency. Summary: LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency. Reviewers: wmi, davidxl, stoklund, zansari, myatsina, RKSimon, DavidKreitzer, mkuper, joerg, spatel Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21560 llvm-svn: 274068
2016-06-29 05:19:34 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_18
; SSE-NEXT: .LBB80_16:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
Relax the clearance calculating for breaking partial register dependency. Summary: LLVM assumes that large clearance will hide the partial register spill penalty. But in our experiment, 16 clearance is too small. As the inserted XOR is normally fairly cheap, we should have a higher clearance threshold to aggressively insert XORs that is necessary to break partial register dependency. Reviewers: wmi, davidxl, stoklund, zansari, myatsina, RKSimon, DavidKreitzer, mkuper, joerg, spatel Subscribers: davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21560 llvm-svn: 274068
2016-06-29 05:19:34 +08:00
; SSE-NEXT: xorps %xmm1, %xmm1
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_18:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
; SSE-NEXT: movd %xmm3, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_19
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#20:
; SSE-NEXT: xorps %xmm3, %xmm3
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_21
; SSE-NEXT: .LBB80_19:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: xorps %xmm3, %xmm3
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_21:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; SSE-NEXT: movd %xmm2, %rax
; SSE-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: js .LBB80_22
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: # BB#23:
; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: jmp .LBB80_24
; SSE-NEXT: .LBB80_22:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: movq %rax, %rcx
; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $1, %eax
; SSE-NEXT: orq %rcx, %rax
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: xorps %xmm2, %xmm2
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; SSE-NEXT: cvtsi2ssq %rax, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: addss %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; SSE-NEXT: .LBB80_24:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_8i64_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vmovdqa 32(%rdi), %ymm2
; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_3
; AVX1-NEXT: .LBB80_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_6
; AVX1-NEXT: .LBB80_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_9
; AVX1-NEXT: .LBB80_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm4, %xmm4, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_12
; AVX1-NEXT: .LBB80_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_12:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_13
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#14:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_15
; AVX1-NEXT: .LBB80_13:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm5, %xmm5, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_15:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_16
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#17:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_18
; AVX1-NEXT: .LBB80_16:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_18:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3]
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vmovq %xmm4, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_19
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#20:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_21
; AVX1-NEXT: .LBB80_19:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_21:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
; AVX1-NEXT: vpextrq $1, %xmm4, %rax
; AVX1-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: js .LBB80_22
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: # BB#23:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: jmp .LBB80_24
; AVX1-NEXT: .LBB80_22:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX1-NEXT: movq %rax, %rcx
; AVX1-NEXT: shrq %rcx
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: orq %rcx, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX1-NEXT: .LBB80_24:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_8i64_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa 32(%rdi), %ymm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#2:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_3
; AVX2-NEXT: .LBB80_1:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_3:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vmovq %xmm2, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#5:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_6
; AVX2-NEXT: .LBB80_4:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_6:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm2
; AVX2-NEXT: vmovq %xmm2, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_7
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#8:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_9
; AVX2-NEXT: .LBB80_7:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm4, %xmm4, %xmm4
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_9:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vpextrq $1, %xmm2, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_10
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#11:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_12
; AVX2-NEXT: .LBB80_10:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_12:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_13
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#14:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_15
; AVX2-NEXT: .LBB80_13:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm5, %xmm5, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_15:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_16
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#17:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_18
; AVX2-NEXT: .LBB80_16:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_18:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3]
; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
; AVX2-NEXT: vmovq %xmm4, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_19
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#20:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_21
; AVX2-NEXT: .LBB80_19:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm5
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_21:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
; AVX2-NEXT: vpextrq $1, %xmm4, %rax
; AVX2-NEXT: testq %rax, %rax
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: js .LBB80_22
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: # BB#23:
Avoid false dependencies of undef machine operands This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref. Pseudo example: loop: xmm0 = ... xmm1 = vcvtsi2sdl eax, xmm0<undef> ... = inst xmm0 jmp loop In this example, selecting xmm0 as the undef register creates false dependency between loop iterations. This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction. Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem. Differential Revision: https://reviews.llvm.org/D22466 llvm-svn: 278321
2016-08-11 15:32:08 +08:00
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: jmp .LBB80_24
; AVX2-NEXT: .LBB80_22:
Recommit 'Remove the restriction that MachineSinking is now stopped by "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
2016-08-12 11:33:22 +08:00
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: shrq %rcx
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: orq %rcx, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
[X86][SSE] Add v2i64 -> v2i32 + zero codegen test llvm-svn: 287813
2016-11-24 05:19:57 +08:00
; AVX2-NEXT: .LBB80_24:
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_8i64_to_8f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; AVX512F-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; AVX512F-NEXT: vmovq %xmm2, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; AVX512F-NEXT: vpextrq $1, %xmm2, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX512F-NEXT: vextracti32x4 $1, %zmm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_8i64_to_8f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; AVX512VL-NEXT: vmovq %xmm2, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX512VL-NEXT: vextracti32x4 $1, %zmm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_8i64_to_8f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vcvtuqq2ps (%rdi), %ymm0
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_8i64_to_8f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtuqq2ps (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i64>, <8 x i64> *%a
%cvt = uitofp <8 x i64> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @uitofp_load_8i32_to_8f32(<8 x i32> *%a) {
; SSE-LABEL: uitofp_load_8i32_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: movdqa 16(%rdi), %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [1258291200,1258291200,1258291200,1258291200]
; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: psrld $16, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm5 = [1392508928,1392508928,1392508928,1392508928]
; SSE-NEXT: por %xmm5, %xmm0
; SSE-NEXT: movaps {{.*#+}} xmm6 = [-5.497642e+11,-5.497642e+11,-5.497642e+11,-5.497642e+11]
; SSE-NEXT: addps %xmm6, %xmm0
; SSE-NEXT: addps %xmm3, %xmm0
; SSE-NEXT: pand %xmm1, %xmm2
; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: psrld $16, %xmm1
; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: addps %xmm6, %xmm1
; SSE-NEXT: addps %xmm2, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_8i32_to_8f32:
; AVX1: # BB#0:
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
[X86] Remove unnecessary bitcast from the front of AVX1Only 256-bit logical operation patterns. llvm-svn: 278088
2016-08-09 11:06:26 +08:00
; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_8i32_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15]
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
; AVX2-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
[X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp opportunities without AVX512VL llvm-svn: 287348
2016-11-18 23:31:36 +08:00
; AVX512F-LABEL: uitofp_load_8i32_to_8f32:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovaps (%rdi), %ymm0
; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: uitofp_load_8i32_to_8f32:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vcvtudq2ps (%rdi), %ymm0
; AVX512VL-NEXT: retq
[X86][AVX512DQ] Add fp <-> int tests for AVX512DQ/AVX512DQ+VL llvm-svn: 287706
2016-11-23 06:04:50 +08:00
;
; AVX512DQ-LABEL: uitofp_load_8i32_to_8f32:
; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
; AVX512DQ-NEXT: retq
;
; AVX512VLDQ-LABEL: uitofp_load_8i32_to_8f32:
; AVX512VLDQ: # BB#0:
; AVX512VLDQ-NEXT: vcvtudq2ps (%rdi), %ymm0
; AVX512VLDQ-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i32>, <8 x i32> *%a
%cvt = uitofp <8 x i32> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @uitofp_load_8i16_to_8f32(<8 x i16> *%a) {
; SSE-LABEL: uitofp_load_8i16_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm1
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_8i16_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_8i16_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_load_8i16_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i16>, <8 x i16> *%a
%cvt = uitofp <8 x i16> %ld to <8 x float>
ret <8 x float> %cvt
}
define <8 x float> @uitofp_load_8i8_to_8f32(<8 x i8> *%a) {
; SSE-LABEL: uitofp_load_8i8_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: uitofp_load_8i8_to_8f32:
; AVX1: # BB#0:
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: uitofp_load_8i8_to_8f32:
; AVX2: # BB#0:
; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: uitofp_load_8i8_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
2016-09-18 20:45:23 +08:00
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
; AVX512-NEXT: retq
[X86][SSE] Added vector sitofp/uitofp folded load tests llvm-svn: 270558
2016-05-24 21:07:23 +08:00
%ld = load <8 x i8>, <8 x i8> *%a
%cvt = uitofp <8 x i8> %ld to <8 x float>
ret <8 x float> %cvt
}
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
;
; Aggregates
;
%Arguments = type <{ <8 x i8>, <8 x i16>, <8 x float>* }>
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
define void @aggregate_sitofp_8i16_to_8f32(%Arguments* nocapture readonly %a0) {
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-LABEL: aggregate_sitofp_8i16_to_8f32:
; SSE: # BB#0:
; SSE-NEXT: movq 24(%rdi), %rax
; SSE-NEXT: movdqu 8(%rdi), %xmm0
[X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
2015-11-14 03:47:43 +08:00
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
[X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
2015-11-14 03:47:43 +08:00
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
[X86][SSE] Combine UNPCKL with vector_shuffle into UNPCKH to save one instruction for sext from v16i8 to v16i16 and v8i16 to v8i32. This patch is enabling combining UNPCKL with vector_shuffle that moves the upper half of a vector into the lower half, into a UNPCKH instruction. For example: t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1, undef:v16i8 t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2 will be combined to: t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1 Differential revision: http://reviews.llvm.org/D14399 llvm-svn: 253067
2015-11-14 03:47:43 +08:00
; SSE-NEXT: movaps %xmm0, 16(%rax)
; SSE-NEXT: movaps %xmm1, (%rax)
Refreshed tests and reordered in descending integer size. llvm-svn: 242610
2015-07-19 00:14:56 +08:00
; SSE-NEXT: retq
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX1-LABEL: aggregate_sitofp_8i16_to_8f32:
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
; AVX1: # BB#0:
; AVX1-NEXT: movq 24(%rdi), %rax
; AVX1-NEXT: vmovdqu 8(%rdi), %xmm0
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-NEXT: vmovaps %ymm0, (%rax)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
[X86][SSE] Updated vector conversion test names. I'll be adding further tests shortly so need a more thorough naming convention. llvm-svn: 242440
2015-07-17 05:00:57 +08:00
; AVX2-LABEL: aggregate_sitofp_8i16_to_8f32:
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
; AVX2: # BB#0:
; AVX2-NEXT: movq 24(%rdi), %rax
; AVX2-NEXT: vpmovsxwd 8(%rdi), %ymm0
; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-NEXT: vmovaps %ymm0, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
[AVX-512] Add AVX512 run line to a test and re-generate the checks. Future commits will refine some of the sequences. llvm-svn: 277932
2016-08-07 03:31:47 +08:00
;
; AVX512-LABEL: aggregate_sitofp_8i16_to_8f32:
; AVX512: # BB#0:
; AVX512-NEXT: movq 24(%rdi), %rax
; AVX512-NEXT: vpmovsxwd 8(%rdi), %ymm0
; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512-NEXT: vmovaps %ymm0, (%rax)
; AVX512-NEXT: retq
[X86][SSE] Fix PerformSExtCombine bug that accessed the wrong return value of an aggregate type. Fix to rL237885 to ensure that it accesses the correct return value of an aggregate type. llvm-svn: 240223
2015-06-21 00:19:24 +08:00
%1 = load %Arguments, %Arguments* %a0, align 1
%2 = extractvalue %Arguments %1, 1
%3 = extractvalue %Arguments %1, 2
%4 = sitofp <8 x i16> %2 to <8 x float>
store <8 x float> %4, <8 x float>* %3, align 32
ret void
}