2018-02-13 23:34:09 +08:00
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# RUN: llc -mtriple=thumbv7-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
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2018-02-22 18:43:57 +08:00
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#
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# This checks alignment of a new block when a big basic block is split up.
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#
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2018-02-13 23:34:09 +08:00
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7-arm--eabi"
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declare i32 @llvm.arm.space(i32, i32) #0
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define dso_local i32 @THUMB(i32 %A.coerce) local_unnamed_addr #1 {
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entry:
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%F = alloca float, align 4
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%S = alloca half, align 2
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%tmp.0.extract.trunc = trunc i32 %A.coerce to i16
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%0 = bitcast i16 %tmp.0.extract.trunc to half
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store volatile float 4.200000e+01, float* %F, align 4
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store volatile half 0xH3C00, half* %S, align 2
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%S.0.S.0.142 = load volatile half, half* %S, align 2
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%1 = call i32 @llvm.arm.space(i32 1230, i32 undef)
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%add42 = fadd half %S.0.S.0.142, 0xH2E66
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store volatile half %add42, half* %S, align 2
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%2 = call i32 @llvm.arm.space(i32 1330, i32 undef)
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%S.0.S.0.119 = load volatile half, half* %S, align 2
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%3 = bitcast half %add42 to i16
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%tmp87.0.insert.ext = zext i16 %3 to i32
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ret i32 %tmp87.0.insert.ext
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}
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attributes #0 = { nounwind }
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attributes #1 = { minsize nounwind optsize "target-features"="+crc,+crypto,+dsp,+fp-armv8,+fullfp16,+hwdiv,+hwdiv-arm,+neon,+ras,+strict-align,+thumb-mode" }
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...
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---
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name: THUMB
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alignment: 1
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tracksRegLiveness: true
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frameInfo:
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stackSize: 8
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maxAlignment: 4
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maxCallFrameSize: 0
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stack:
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2019-06-17 17:13:29 +08:00
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- { id: 0, name: F, offset: -4, size: 4, alignment: 4, stack-id: default, local-offset: -4 }
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- { id: 1, name: S, offset: -6, size: 2, alignment: 2, stack-id: default, local-offset: -6 }
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2018-02-13 23:34:09 +08:00
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constants:
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- id: 0
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value: i32 1109917696
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alignment: 4
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- id: 1
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value: half 0xH2E66
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alignment: 2
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#CHECK: t2B %[[BB3:bb.[0-9]]]
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#CHECK: bb.{{.}} (align 2):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY 2, %const.{{.}}, 4
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#CHECK: bb.{{.}} (align 1):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY 3, %const.{{.}}, 2
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#CHECK: [[BB3]].entry (align 1):
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body: |
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bb.0.entry:
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$sp = frame-setup tSUBspi $sp, 2, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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renamable $r0 = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
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renamable $s0 = FCONSTH 112, 14, $noreg
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tSTRspi killed renamable $r0, $sp, 1, 14, $noreg :: (volatile store 4 into %ir.F)
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VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
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renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
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renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load 2 from constant-pool)
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dead renamable $r0 = SPACE 1230, undef renamable $r0
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renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg
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VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
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renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg
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dead renamable $r1 = SPACE 1330, undef renamable $r0
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dead renamable $s0 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
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$sp = tADDspi $sp, 2, 14, $noreg
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tBX_RET 14, $noreg, implicit killed $r0
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...
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