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llvm-project/llvm/test/CodeGen/ARM/thumb2-it-block.ll

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Be less conservative about forming IT blocks. In http://reviews.llvm.org/rL215382, IT forming was made more conservative under the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M. But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block as long as the flags register is dead afterwards. This gives significant performance improvements in a variety of MPEG based workloads. Differential revision: http://reviews.llvm.org/D11680 llvm-svn: 243869
2015-08-03 17:24:48 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s
Add testcase for PR11107. llvm-svn: 141607
2011-10-11 08:26:57 +08:00
; PR11107
Test simplification that Ana Pazos noticed. llvm-svn: 141644
2011-10-11 12:43:15 +08:00
define i32 @test(i32 %a, i32 %b) {
Add testcase for PR11107. llvm-svn: 141607
2011-10-11 08:26:57 +08:00
entry:
Test simplification that Ana Pazos noticed. llvm-svn: 141644
2011-10-11 12:43:15 +08:00
%cmp1 = icmp slt i32 %a, 0
%sub1 = sub nsw i32 0, %a
%abs1 = select i1 %cmp1, i32 %sub1, i32 %a
%cmp2 = icmp slt i32 %b, 0
%sub2 = sub nsw i32 0, %b
%abs2 = select i1 %cmp2, i32 %sub2, i32 %b
%add = add nsw i32 %abs1, %abs2
ret i32 %add
Add testcase for PR11107. llvm-svn: 141607
2011-10-11 08:26:57 +08:00
}
ARM: try harder to detect non-IT eligible instructions For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
2014-08-12 04:13:25 +08:00
Be less conservative about forming IT blocks. In http://reviews.llvm.org/rL215382, IT forming was made more conservative under the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M. But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block as long as the flags register is dead afterwards. This gives significant performance improvements in a variety of MPEG based workloads. Differential revision: http://reviews.llvm.org/D11680 llvm-svn: 243869
2015-08-03 17:24:48 +08:00
; CHECK: cmp
; CHECK-NEXT: it mi
; We shouldn't need to check for the extra 's' here; tRSB should be printed as
; "rsb" inside an IT block, not "rsbs".
; CHECK-NEXT: rsb{{s?}}mi
; CHECK-NEXT: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsb{{s?}}mi
ARM: try harder to detect non-IT eligible instructions For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
2014-08-12 04:13:25 +08:00