maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Mips/mips64r6/valid.s

279 lines
24 KiB
ArmAsm
Raw Normal View History

[mips][mips64r6] Added mul/mulu/muh/muhu Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
2014-05-12 23:12:45 +08:00
# Instructions that are valid
#
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
# Branches have some unusual encoding rules in MIPS32r6 so we need to test:
# rs == 0
# rs != 0
# rt == 0
# rt != 0
# rs < rt
# rs == rt
# rs > rt
# appropriately for each branch instruction
#
[mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6 Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 llvm-svn: 211021
2014-06-16 21:25:35 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s
# RUN: FileCheck %s -check-prefix=WARNING < %t0
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
a:
[mips][mips64r6] Added mul/mulu/muh/muhu Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
2014-05-12 23:12:45 +08:00
.set noat
# FIXME: Add the instructions carried forward from older ISA's
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
[mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
2014-09-16 18:19:03 +08:00
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
[mips][mips64r6] Add align and dalign Summary: Depends on D3689 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3728 llvm-svn: 208872
2014-05-15 20:06:36 +08:00
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
Reland r306095: [mips] Fix reg positions in the aui/daui instructions After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
2017-06-24 06:37:19 +08:00
aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x43,0x00,0x17]
[mips][mips64r6] Add addiupc, aluipc, and auipc Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
2014-05-15 18:45:58 +08:00
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
[mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
2014-06-13 21:02:52 +08:00
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
[mips][mips64r6] Add bc[12](eq|ne)z Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
2014-05-21 20:56:39 +08:00
bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01]
bc1eqz $f31,4 # CHECK: bc1eqz $f31, 4 # encoding: [0x45,0x3f,0x00,0x01]
bc1nez $f0,4 # CHECK: bc1nez $f0, 4 # encoding: [0x45,0xa0,0x00,0x01]
bc1nez $f31,4 # CHECK: bc1nez $f31, 4 # encoding: [0x45,0xbf,0x00,0x01]
bc2eqz $0,8 # CHECK: bc2eqz $0, 8 # encoding: [0x49,0x20,0x00,0x02]
bc2eqz $31,8 # CHECK: bc2eqz $31, 8 # encoding: [0x49,0x3f,0x00,0x02]
bc2nez $0,8 # CHECK: bc2nez $0, 8 # encoding: [0x49,0xa0,0x00,0x02]
bc2nez $31,8 # CHECK: bc2nez $31, 8 # encoding: [0x49,0xbf,0x00,0x02]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
# beqc requires rs < rt && rs != 0 but we accept this and fix it. See also bovc.
beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
beqc $6, $5, 256 # CHECK: beqc $6, $5, 256 # encoding: [0x20,0xa6,0x00,0x40]
[mips][mips64r6] Add Compact zero-compare branch-and-link instructions Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
2014-05-16 20:27:19 +08:00
beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d]
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90]
[mips][mips64r6] Add bgec and bgeuc instructions Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
2014-06-12 19:47:44 +08:00
bgec $2, $3, 256 # CHECK: bgec $2, $3, 256 # encoding: [0x58,0x43,0x00,0x40]
bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40]
[mips][mips64r6] Add Compact zero-compare branch-and-link instructions Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
2014-05-16 20:27:19 +08:00
bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d]
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40]
[mips][mips64r6] Add Compact zero-compare branch-and-link instructions Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
2014-05-16 20:27:19 +08:00
bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d]
[mips][mips64r6] Add compact branch instructions Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
2014-05-16 19:03:45 +08:00
bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40]
[mips][mips64r6] Add bitswap, and dbitswap Summary: Depends on D3728 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3729 llvm-svn: 208877
2014-05-15 20:18:23 +08:00
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
[mips][mips64r6] Add Compact zero-compare branch-and-link instructions Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
2014-05-16 20:27:19 +08:00
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40]
[mips][mips64r6] Add BLTC and BLTUC instructions Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
2014-06-18 22:36:00 +08:00
bltc $5, $6, 256 # CHECK: bltc $5, $6, 256 # encoding: [0x5c,0xa6,0x00,0x40]
bltuc $5, $6, 256 # CHECK: bltuc $5, $6, 256 # encoding: [0x1c,0xa6,0x00,0x40]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d]
bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
# bnec requires rs < rt && rs != 0 but we accept this and fix it. See also bnvc.
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
bnec $6, $5, 256 # CHECK: bnec $6, $5, 256 # encoding: [0x60,0xa6,0x00,0x40]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d]
bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
# bnvc requires that rs >= rt but we accept both and fix this. See also bnec.
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01]
bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
bnvc $2, $4, 4 # CHECK: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01]
# bovc requires that rs >= rt but we accept both and fix this. See also beqc.
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01]
bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01]
[mips] Enforce compact branch register restrictions Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
2016-06-01 01:34:42 +08:00
bovc $2, $4, 4 # CHECK: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01]
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b]
class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
2014-07-09 18:40:20 +08:00
cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
[mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmt Differential Revision: http://reviews.llvm.org/D3750 llvm-svn: 208970
2014-05-16 17:48:29 +08:00
cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
2014-07-09 18:40:20 +08:00
cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86]
cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84]
cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
2014-07-09 18:40:20 +08:00
cmp.saf.d $f2,$f3,$f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.saf.s $f2,$f3,$f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88]
[mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmt Differential Revision: http://reviews.llvm.org/D3750 llvm-svn: 208970
2014-05-16 17:48:29 +08:00
cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
2014-07-09 18:40:20 +08:00
cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.sle.s $f2,$f3,$f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e]
cmp.slt.d $f2,$f3,$f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c]
cmp.slt.s $f2,$f3,$f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c]
cmp.sueq.d $f2,$f3,$f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b]
cmp.sueq.s $f2,$f3,$f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
2014-07-09 18:40:20 +08:00
cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
cmp.sult.d $f2,$f3,$f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d]
cmp.sult.s $f2,$f3,$f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d]
cmp.sun.d $f2,$f3,$f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89]
cmp.sun.s $f2,$f3,$f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89]
cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83]
cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83]
cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87]
cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87]
cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85]
cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85]
cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81]
cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81]
[mips] Fix aui/daui/dahi/dati for MIPSR6 For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
2016-10-14 17:31:42 +08:00
daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
dahi $3, $3, 0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
dati $3, $3, 0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
Reland r306095: [mips] Fix reg positions in the aui/daui instructions After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
2017-06-24 06:37:19 +08:00
daui $3, $2, 0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x43,0x12,0x34]
[mips][mips64r6] Add b[on]vc Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
2014-05-22 19:23:21 +08:00
dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ddiv $2,$3,$4 # CHECK: ddiv $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9e]
ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
[mips] Marked the DI/EI instruction aliases as MIPS32r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
2014-10-16 23:23:52 +08:00
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
[mips][mips64r6] Sorted *_ENC, *_DESC classes and tests Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
2014-05-19 22:57:46 +08:00
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
[mips][ias] Range check uimm2 operands and fix a bug this revealed. Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
2015-11-06 20:22:31 +08:00
dlsa $2, $3, $4, 3 # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x95]
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
dmfc0 $10, $16, 2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde]
dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
dmtc0 $4, $10, 0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdc]
dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9c]
dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
[mips][msa] Test basic operations for the N32 ABI too. Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
2015-05-05 16:48:35 +08:00
dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e]
dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e]
dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f]
[mips] Marked the DADDiu instruction aliases as MIPS III. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
2014-09-15 22:47:46 +08:00
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
[mips] Add IAS support for dvp, evp These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
2016-10-13 20:12:56 +08:00
dvp $4 # CHECK: dvp $4 # encoding: [0x41,0x64,0x00,0x24]
dvp # CHECK: dvp $zero # encoding: [0x41,0x60,0x00,0x24]
[mips] Marked the DI/EI instruction aliases as MIPS32r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
2014-10-16 23:23:52 +08:00
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
[mips] Added support for the ERETNC instruction. Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
2015-07-20 20:28:56 +08:00
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
[mips] Add IAS support for dvp, evp These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
2016-10-13 20:12:56 +08:00
evp $5 # CHECK: evp $5 # encoding: [0x41,0x65,0x00,0x04]
evp # CHECK: evp $zero # encoding: [0x41,0x60,0x00,0x04]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
[mips] Never select JAL for calls to an absolute immediate address. Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
2016-01-11 23:57:46 +08:00
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 llvm-svn: 265134
2016-04-01 19:55:33 +08:00
jr $ra # CHECK: jr $ra # encoding: [0x03,0xe0,0x00,0x09]
jr $25 # CHECK: jr $25 # encoding: [0x03,0x20,0x00,0x09]
Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
2016-04-14 21:43:17 +08:00
jrc $27 # CHECK: jrc $27 # encoding: [0xd8,0x1b,0x00,0x00]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
2016-04-14 21:43:17 +08:00
jalrc $25 # CHECK: jalrc $25 # encoding: [0xf8,0x19,0x00,0x00]
Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
2014-05-20 22:46:24 +08:00
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
[mips] Add l.[sd] and s.[sd] instruction aliases Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
2016-08-17 22:45:09 +08:00
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
[mips][mips64r6] Add LDPC instruction Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
2014-06-09 17:49:51 +08:00
ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37]
[mips][ias] Range check uimm2 operands and fix a bug this revealed. Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
2015-11-06 20:22:31 +08:00
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
2014-05-20 22:46:24 +08:00
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
[mips][mips64r6] Add Floating Point Fused Multiply Add Subtract Differential Revision: http://reviews.llvm.org/D3727 llvm-svn: 208952
2014-05-16 16:42:27 +08:00
maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98]
[mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions Differential Revision: http://reviews.llvm.org/D3709 llvm-svn: 208890
2014-05-15 22:54:06 +08:00
max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
[mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions Differential Revision: http://reviews.llvm.org/D3709 llvm-svn: 208890
2014-05-15 22:54:06 +08:00
maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
[mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions Differential Revision: http://reviews.llvm.org/D3709 llvm-svn: 208890
2014-05-15 22:54:06 +08:00
mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
[mips] Remap move as or. Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
2015-08-11 16:56:25 +08:00
move $a0,$a3 # CHECK: move $4, $7 # encoding: [0x00,0xe0,0x20,0x25]
move $s5,$a0 # CHECK: move $21, $4 # encoding: [0x00,0x80,0xa8,0x25]
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99]
msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99]
muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8]
muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9]
mul $2,$3,$4 # CHECK: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98]
mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99]
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
[mips] not instruction alias This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
2016-11-16 19:04:49 +08:00
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
[mips] Implement alias for 'and' and 'or' instructions for all ISAs. Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
2014-06-18 21:30:57 +08:00
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
Recommit "[mips] Add names and tests for the hardware registers" The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
2014-11-11 18:31:31 +08:00
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
2014-05-20 22:46:24 +08:00
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a]
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
[mips] Add l.[sd] and s.[sd] instruction aliases Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
2016-08-17 22:45:09 +08:00
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
[mips] Added support for assembling sdbbp. Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
2014-06-24 21:00:32 +08:00
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
[mips] seb, seh instruction aliases Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
2016-11-23 03:17:23 +08:00
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
[mips] SYNC $stype instruction was added in Mips32 but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
2014-06-19 01:10:30 +08:00
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
[mips] Range check uimm20 and fixed a bug this revealed. Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
2016-03-01 00:06:38 +08:00
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
[mips] Marked the Trap-on-Condition instructions as Mips II Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
2014-09-05 23:50:13 +08:00
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
[mips] Marked the Trap-on-Condition instructions as Mips II Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
2014-09-05 23:50:13 +08:00
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
[mips][mips64r6] Sorted instructions in test. NFC. llvm-svn: 236221
2015-04-30 18:23:48 +08:00
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
[mips] Marked the Trap-on-Condition instructions as Mips II Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
2014-09-05 23:50:13 +08:00
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
2015-03-17 21:17:44 +08:00
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
1:
[mips] Weaken asm predicate for memory offsets The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
2016-05-27 21:56:36 +08:00
# Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
lh $3, %lo(g_8)($2) # CHECK: encoding: [0x84,0x43,A,A]
lhu $3, %lo(g_8)($2) # CHECK: encoding: [0x94,0x43,A,A]
lw $3, %lo(g_8)($2) # CHECK: encoding: [0x8c,0x43,A,A]
sb $3, %lo(g_8)($2) # CHECK: encoding: [0xa0,0x43,A,A]
sh $3, %lo(g_8)($2) # CHECK: encoding: [0xa4,0x43,A,A]
sw $3, %lo(g_8)($2) # CHECK: encoding: [0xac,0x43,A,A]
lwc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xc4,0x40,A,A]
ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
swc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xe4,0x40,A,A]
sdc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xf4,0x40,A,A]
lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
ld $3, %lo(g_8)($2) # CHECK: encoding: [0xdc,0x43,A,A]
sd $3, %lo(g_8)($2) # CHECK: encoding: [0xfc,0x43,A,A]
.type g_8,@object
.comm g_8,16,16