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llvm-project/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

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[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
2016-10-04 19:25:52 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
Add VSX Scalar loads and stores to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
2015-05-08 02:24:05 +08:00
@d = common global double 0.000000e+00, align 8
@f = common global float 0.000000e+00, align 4
@i = common global i32 0, align 4
@ui = common global i32 0, align 4
; Function Attrs: nounwind
define void @dblToInt() #0 {
entry:
%ii = alloca i32, align 4
%0 = load double, double* @d, align 8
%conv = fptosi double %0 to i32
store volatile i32 %conv, i32* %ii, align 4
ret void
; CHECK-LABEL: @dblToInt
; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
; CHECK: stxsiwx [[REGCONV1]],
}
; Function Attrs: nounwind
define void @fltToInt() #0 {
entry:
%ii = alloca i32, align 4
%0 = load float, float* @f, align 4
%conv = fptosi float %0 to i32
store volatile i32 %conv, i32* %ii, align 4
ret void
; CHECK-LABEL: @fltToInt
; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
; CHECK: stxsiwx [[REGCONV2]],
}
; Function Attrs: nounwind
define void @intToDbl() #0 {
entry:
%dd = alloca double, align 8
%0 = load i32, i32* @i, align 4
%conv = sitofp i32 %0 to double
store volatile double %conv, double* %dd, align 8
ret void
; CHECK-LABEL: @intToDbl
; CHECK: lxsiwax [[REGLD1:[0-9]+]],
; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
}
; Function Attrs: nounwind
define void @intToFlt() #0 {
entry:
%ff = alloca float, align 4
%0 = load i32, i32* @i, align 4
%conv = sitofp i32 %0 to float
store volatile float %conv, float* %ff, align 4
ret void
; CHECK-LABEL: @intToFlt
; CHECK: lxsiwax [[REGLD2:[0-9]+]],
Scalar to vector conversions using direct moves This patch corresponds to review: http://reviews.llvm.org/D11471 It improves the code generated for converting a scalar to a vector value. With direct moves from GPRs to VSRs, we no longer require expensive stack operations for this. Subsequent patches will handle the reverse case and more general operations between vectors and their scalar elements. llvm-svn: 244921
2015-08-14 01:40:44 +08:00
; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]]
Add VSX Scalar loads and stores to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
2015-05-08 02:24:05 +08:00
}
; Function Attrs: nounwind
define void @dblToUInt() #0 {
entry:
%uiui = alloca i32, align 4
%0 = load double, double* @d, align 8
%conv = fptoui double %0 to i32
store volatile i32 %conv, i32* %uiui, align 4
ret void
; CHECK-LABEL: @dblToUInt
; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
; CHECK: stxsiwx [[REGCONV3]],
}
; Function Attrs: nounwind
define void @fltToUInt() #0 {
entry:
%uiui = alloca i32, align 4
%0 = load float, float* @f, align 4
%conv = fptoui float %0 to i32
store volatile i32 %conv, i32* %uiui, align 4
ret void
; CHECK-LABEL: @fltToUInt
; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
; CHECK: stxsiwx [[REGCONV4]],
}
; Function Attrs: nounwind
define void @uIntToDbl() #0 {
entry:
%dd = alloca double, align 8
%0 = load i32, i32* @ui, align 4
%conv = uitofp i32 %0 to double
store volatile double %conv, double* %dd, align 8
ret void
; CHECK-LABEL: @uIntToDbl
; CHECK: lxsiwzx [[REGLD3:[0-9]+]],
; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
}
; Function Attrs: nounwind
define void @uIntToFlt() #0 {
entry:
%ff = alloca float, align 4
%0 = load i32, i32* @ui, align 4
%conv = uitofp i32 %0 to float
store volatile float %conv, float* %ff, align 4
ret void
; CHECK-LABEL: @uIntToFlt
; CHECK: lxsiwzx [[REGLD4:[0-9]+]],
Scalar to vector conversions using direct moves This patch corresponds to review: http://reviews.llvm.org/D11471 It improves the code generated for converting a scalar to a vector value. With direct moves from GPRs to VSRs, we no longer require expensive stack operations for this. Subsequent patches will handle the reverse case and more general operations between vectors and their scalar elements. llvm-svn: 244921
2015-08-14 01:40:44 +08:00
; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]]
Add VSX Scalar loads and stores to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
2015-05-08 02:24:05 +08:00
}
; Function Attrs: nounwind
define void @dblToFloat() #0 {
entry:
%ff = alloca float, align 4
%0 = load double, double* @d, align 8
%conv = fptrunc double %0 to float
store volatile float %conv, float* %ff, align 4
ret void
; CHECK-LABEL: @dblToFloat
; CHECK: lxsdx [[REGLD5:[0-9]+]],
; CHECK: stxsspx [[REGLD5]],
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
2016-10-04 19:25:52 +08:00
; CHECK-P9-LABEL: @dblToFloat
; CHECK-P9: lfd [[REGLD5:[0-9]+]],
; CHECK-P9: stfs [[REGLD5]],
Add VSX Scalar loads and stores to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
2015-05-08 02:24:05 +08:00
}
; Function Attrs: nounwind
define void @floatToDbl() #0 {
entry:
%dd = alloca double, align 8
%0 = load float, float* @f, align 4
%conv = fpext float %0 to double
store volatile double %conv, double* %dd, align 8
ret void
; CHECK-LABEL: @floatToDbl
; CHECK: lxsspx [[REGLD5:[0-9]+]],
; CHECK: stxsdx [[REGLD5]],
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
2016-10-04 19:25:52 +08:00
; CHECK-P9-LABEL: @floatToDbl
; CHECK-P9: lfs [[REGLD5:[0-9]+]],
; CHECK-P9: stfd [[REGLD5]],
Add VSX Scalar loads and stores to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9440 It adds a new register class to the PPC back end to contain single precision values in VSX registers. Additionally, it adds scalar loads and stores for VSX registers. llvm-svn: 236755
2015-05-08 02:24:05 +08:00
}