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llvm-project/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s
[PowerPC] Reuse a load operand in int->fp conversions int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
2015-01-07 06:31:02 +08:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
define double @test1(i64* nocapture readonly %x) #0 {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i64, i64* %x, align 8
[PowerPC] Reuse a load operand in int->fp conversions int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
2015-01-07 06:31:02 +08:00
%conv = sitofp i64 %0 to double
ret double %conv
; CHECK-LABEL: @test1
; CHECK: lfd [[REG1:[0-9]+]], 0(3)
; CHECK: fcfid 1, [[REG1]]
; CHECK: blr
}
; Function Attrs: nounwind readonly
define double @test2(i32* nocapture readonly %x) #0 {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %x, align 4
[PowerPC] Reuse a load operand in int->fp conversions int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
2015-01-07 06:31:02 +08:00
%conv = sitofp i32 %0 to double
ret double %conv
; CHECK-LABEL: @test2
; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3
; CHECK: fcfid 1, [[REG1]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define float @foo(float %X) #0 {
entry:
%conv = fptosi float %X to i32
%conv1 = sitofp i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foo
; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
; CHECK: stfiwx [[REG2]], 0, [[REG1]]
; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
; CHECK: fcfids 1, [[REG3]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define double @food(double %X) #0 {
entry:
%conv = fptosi double %X to i32
%conv1 = sitofp i32 %conv to double
ret double %conv1
; CHECK-LABEL: @food
; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
; CHECK: stfiwx [[REG2]], 0, [[REG1]]
; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
; CHECK: fcfid 1, [[REG3]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define float @foou(float %X) #0 {
entry:
%conv = fptoui float %X to i32
%conv1 = uitofp i32 %conv to float
ret float %conv1
; CHECK-LABEL: @foou
; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
; CHECK: stfiwx [[REG2]], 0, [[REG1]]
; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
; CHECK: fcfidus 1, [[REG3]]
; CHECK: blr
}
; Function Attrs: nounwind readnone
define double @fooud(double %X) #0 {
entry:
%conv = fptoui double %X to i32
%conv1 = uitofp i32 %conv to double
ret double %conv1
; CHECK-LABEL: @fooud
; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
; CHECK: stfiwx [[REG2]], 0, [[REG1]]
; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
; CHECK: fcfidu 1, [[REG3]]
; CHECK: blr
}
attributes #0 = { nounwind readonly }