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llvm-project/llvm/test/CodeGen/ARM/negate-i1.ll

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[ARM] add tests for PR30660 llvm-svn: 284280
2016-10-15 04:52:43 +08:00
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; PR30660 - https://llvm.org/bugs/show_bug.cgi?id=30660
define i32 @select_i32_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i32_neg1_or_0:
; CHECK-NEXT: @ BB#0:
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsb r0, r0, #0
[ARM] add tests for PR30660 llvm-svn: 284280
2016-10-15 04:52:43 +08:00
; CHECK-NEXT: mov pc, lr
;
%b = sext i1 %a to i32
ret i32 %b
}
define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
; CHECK-NEXT: @ BB#0:
[DAG] optimize negation of bool Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
2016-10-20 00:58:59 +08:00
; CHECK-NEXT: rsb r0, r0, #0
[ARM] add tests for PR30660 llvm-svn: 284280
2016-10-15 04:52:43 +08:00
; CHECK-NEXT: mov pc, lr
;
%b = sext i1 %a to i32
ret i32 %b
}