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llvm-project/llvm/test/CodeGen/ARM/div.ll

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[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI
[ARM] Add support for armv7ve triple in llvm (PR31358). Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
2017-02-10 07:29:14 +08:00
; RUN: llc < %s -mtriple=armv7ve-none-linux-gnu | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=thumbv7ve-none-linux-gnu | \
; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV \
; RUN: -check-prefix=CHECK-THUMB
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f1(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-LABEL: f1
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: __divsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
[ARM] Add support for armv7ve triple in llvm (PR31358). Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
2017-02-10 07:29:14 +08:00
; CHECK-THUMB: .thumb_func
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: sdiv
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-EABI: __aeabi_idiv
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f2(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-LABEL: f2
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: __udivsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
[ARM] Add support for armv7ve triple in llvm (PR31358). Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
2017-02-10 07:29:14 +08:00
; CHECK-THUMB: .thumb_func
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: udiv
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-EABI: __aeabi_uidiv
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f3(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-LABEL: f3
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: __modsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
[ARM] Add support for armv7ve triple in llvm (PR31358). Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
2017-02-10 07:29:14 +08:00
; CHECK-THUMB: .thumb_func
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: sdiv
; CHECK-HWDIV: mls
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; EABI MODE = Remainder in R1, quotient in R0
; CHECK-EABI: __aeabi_idivmod
; CHECK-EABI-NEXT: mov r0, r1
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f4(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; CHECK-LABEL: f4
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: __umodsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
[ARM] Add support for armv7ve triple in llvm (PR31358). Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
2017-02-10 07:29:14 +08:00
; CHECK-THUMB: .thumb_func
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: udiv
; CHECK-HWDIV: mls
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
; EABI MODE = Remainder in R1, quotient in R0
; CHECK-EABI: __aeabi_uidivmod
; CHECK-EABI-NEXT: mov r0, r1
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
[ARM] Use AEABI helpers for i64 div and rem Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
2015-08-24 17:17:18 +08:00
define i64 @f5(i64 %a, i64 %b) {
entry:
; CHECK-LABEL: f5
; CHECK-SWDIV: __moddi3
; CHECK-HWDIV: __moddi3
; EABI MODE = Remainder in R2-R3, quotient in R0-R1
; CHECK-EABI: __aeabi_ldivmod
; CHECK-EABI-NEXT: mov r0, r2
; CHECK-EABI-NEXT: mov r1, r3
%tmp1 = srem i64 %a, %b ; <i64> [#uses=1]
ret i64 %tmp1
}
define i64 @f6(i64 %a, i64 %b) {
entry:
; CHECK-LABEL: f6
; CHECK-SWDIV: __umoddi3
; CHECK-HWDIV: __umoddi3
; EABI MODE = Remainder in R2-R3, quotient in R0-R1
; CHECK-EABI: __aeabi_uldivmod
; CHECK-EABI-NEXT: mov r0, r2
; CHECK-EABI-NEXT: mov r1, r3
%tmp1 = urem i64 %a, %b ; <i64> [#uses=1]
ret i64 %tmp1
}