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llvm-project/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll

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Do some peephole optimizations to remove pointless VMOVs from Neon to integer registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
2011-04-02 10:40:43 +08:00
; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s
; CHECK: function1
Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. llvm-svn: 129345
2011-04-12 10:24:17 +08:00
; CHECK-NOT: vmov
Do some peephole optimizations to remove pointless VMOVs from Neon to integer registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
2011-04-02 10:40:43 +08:00
define double @function1(double %a, double %b, double %c, double %d, double %e, double %f) nounwind noinline ssp {
entry:
%call = tail call double @function2(double %f, double %e, double %d, double %c, double %b, double %a) nounwind
ret double %call
}
declare double @function2(double, double, double, double, double, double)