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llvm-project/llvm/test/MC/AMDGPU/sopp.s

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AMDGPU: Add instruction definitions for VGPR indexing VI added a second method of indexing into VGPRs besides using v_movrel* llvm-svn: 284027
2016-10-13 02:00:51 +08:00
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI %s
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
// Edge Cases
//===----------------------------------------------------------------------===//
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_nop 0
// GCN: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
s_nop 0xffff
// GCN: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf]
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_nop 1
// GCN: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]
s_endpgm
// GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
s_branch 2
// GCN: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf]
s_cbranch_scc0 3
// GCN: s_cbranch_scc0 3 ; encoding: [0x03,0x00,0x84,0xbf]
s_cbranch_scc1 4
// GCN: s_cbranch_scc1 4 ; encoding: [0x04,0x00,0x85,0xbf]
s_cbranch_vccz 5
// GCN: s_cbranch_vccz 5 ; encoding: [0x05,0x00,0x86,0xbf]
s_cbranch_vccnz 6
// GCN: s_cbranch_vccnz 6 ; encoding: [0x06,0x00,0x87,0xbf]
s_cbranch_execz 7
// GCN: s_cbranch_execz 7 ; encoding: [0x07,0x00,0x88,0xbf]
s_cbranch_execnz 8
// GCN: s_cbranch_execnz 8 ; encoding: [0x08,0x00,0x89,0xbf]
[AMDGPU][MC] Fix for Bug 28158 + LIT tests Added support of the following instructions: - s_cbranch_cdbgsys - s_cbranch_cdbgsys_and_user - s_cbranch_cdbgsys_or_user - s_cbranch_cdbguser - s_setkill Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31469 llvm-svn: 299567
2017-04-06 01:26:45 +08:00
s_cbranch_cdbgsys 9
// GCN: s_cbranch_cdbgsys 9 ; encoding: [0x09,0x00,0x97,0xbf]
s_cbranch_cdbgsys_and_user 10
// GCN: s_cbranch_cdbgsys_and_user 10 ; encoding: [0x0a,0x00,0x9a,0xbf]
s_cbranch_cdbgsys_or_user 11
// GCN: s_cbranch_cdbgsys_or_user 11 ; encoding: [0x0b,0x00,0x99,0xbf]
s_cbranch_cdbguser 12
// GCN: s_cbranch_cdbguser 12 ; encoding: [0x0c,0x00,0x98,0xbf]
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_barrier
// GCN: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
//===----------------------------------------------------------------------===//
// s_waitcnt
//===----------------------------------------------------------------------===//
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_waitcnt 0
// GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)
// GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
// GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0)
// GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
s_waitcnt vmcnt(1)
// GCN: s_waitcnt vmcnt(1) ; encoding: [0x71,0x0f,0x8c,0xbf]
s_waitcnt vmcnt(9)
// GCN: s_waitcnt vmcnt(9) ; encoding: [0x79,0x0f,0x8c,0xbf]
s_waitcnt expcnt(2)
// GCN: s_waitcnt expcnt(2) ; encoding: [0x2f,0x0f,0x8c,0xbf]
s_waitcnt lgkmcnt(3)
// GCN: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]
s_waitcnt lgkmcnt(9)
// GCN: s_waitcnt lgkmcnt(9) ; encoding: [0x7f,0x09,0x8c,0xbf]
s_waitcnt vmcnt(0), expcnt(0)
// GCN: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x0f,0x8c,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_sethalt 9
// GCN: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU][MC] Fix for Bug 28158 + LIT tests Added support of the following instructions: - s_cbranch_cdbgsys - s_cbranch_cdbgsys_and_user - s_cbranch_cdbgsys_or_user - s_cbranch_cdbguser - s_setkill Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31469 llvm-svn: 299567
2017-04-06 01:26:45 +08:00
s_setkill 7
// GCN: s_setkill 7 ; encoding: [0x07,0x00,0x8b,0xbf]
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_sleep 10
// GCN: s_sleep 10 ; encoding: [0x0a,0x00,0x8e,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_setprio 1
// GCN: s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf]
AMDGPU: waitcnt operand fixes Summary: Allow lgkmcnt up to 0xF (hardware allows that). Fix mask for ExpCnt in AMDGPUInstPrinter. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16314 Patch by: Nikolay Haustov llvm-svn: 259059
2016-01-29 01:13:44 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_sendmsg 2
[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 llvm-svn: 268762
2016-05-07 01:48:48 +08:00
// GCN: s_sendmsg 2 ; encoding: [0x02,0x00,0x90,0xbf]
s_sendmsg 0x1
// GCN: s_sendmsg sendmsg(MSG_INTERRUPT) ; encoding: [0x01,0x00,0x90,0xbf]
s_sendmsg sendmsg(1)
// GCN: s_sendmsg sendmsg(MSG_INTERRUPT) ; encoding: [0x01,0x00,0x90,0xbf]
s_sendmsg sendmsg(MSG_INTERRUPT)
// GCN: s_sendmsg sendmsg(MSG_INTERRUPT) ; encoding: [0x01,0x00,0x90,0xbf]
s_sendmsg 0x12
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 0) ; encoding: [0x12,0x00,0x90,0xbf]
s_sendmsg sendmsg(2, 1)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 0) ; encoding: [0x12,0x00,0x90,0xbf]
s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 0)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 0) ; encoding: [0x12,0x00,0x90,0xbf]
s_sendmsg 0x122
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 1) ; encoding: [0x22,0x01,0x90,0xbf]
s_sendmsg sendmsg(2, 2, 1)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 1) ; encoding: [0x22,0x01,0x90,0xbf]
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 1)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 1) ; encoding: [0x22,0x01,0x90,0xbf]
s_sendmsg 0x232
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) ; encoding: [0x32,0x02,0x90,0xbf]
s_sendmsg sendmsg(2, 3, 2)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) ; encoding: [0x32,0x02,0x90,0xbf]
s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
// GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) ; encoding: [0x32,0x02,0x90,0xbf]
s_sendmsg 0x3
// GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) ; encoding: [0x03,0x00,0x90,0xbf]
s_sendmsg sendmsg(3, 0)
// GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) ; encoding: [0x03,0x00,0x90,0xbf]
s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
// GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) ; encoding: [0x03,0x00,0x90,0xbf]
s_sendmsg 0x4
// GCN: s_sendmsg 4 ; encoding: [0x04,0x00,0x90,0xbf]
s_sendmsg 11
// GCN: s_sendmsg 11 ; encoding: [0x0b,0x00,0x90,0xbf]
s_sendmsg 0x1f
// GCN: s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_ECC_ERR_INTERRUPT) ; encoding: [0x1f,0x00,0x90,0xbf]
s_sendmsg sendmsg(15, 1)
// GCN: s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_ECC_ERR_INTERRUPT) ; encoding: [0x1f,0x00,0x90,0xbf]
s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_ECC_ERR_INTERRUPT)
// GCN: s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_ECC_ERR_INTERRUPT) ; encoding: [0x1f,0x00,0x90,0xbf]
s_sendmsg 0x6f
// GCN: s_sendmsg 111 ; encoding: [0x6f,0x00,0x90,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_sendmsghalt 3
[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 llvm-svn: 268762
2016-05-07 01:48:48 +08:00
// GCN: s_sendmsghalt sendmsg(MSG_GS_DONE, GS_OP_NOP) ; encoding: [0x03,0x00,0x91,0xbf]
s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT, 1)
// GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT, 1) ; encoding: [0x22,0x01,0x91,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_trap 4
// GCN: s_trap 4 ; encoding: [0x04,0x00,0x92,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_icache_inv
// GCN: s_icache_inv ; encoding: [0x00,0x00,0x93,0xbf]
AMDGPU: waitcnt operand fixes Summary: Allow lgkmcnt up to 0xF (hardware allows that). Fix mask for ExpCnt in AMDGPUInstPrinter. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16314 Patch by: Nikolay Haustov llvm-svn: 259059
2016-01-29 01:13:44 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_incperflevel 5
// GCN: s_incperflevel 5 ; encoding: [0x05,0x00,0x94,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_decperflevel 6
// GCN: s_decperflevel 6 ; encoding: [0x06,0x00,0x95,0xbf]
R600/SI: Start implementing an assembler This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
2014-11-14 22:08:00 +08:00
[AMDGPU] Assembler: Update SOP* tests Add VI encodings. Reformat sopp.s to match style of other files. Differential Revision: http://reviews.llvm.org/D18084 llvm-svn: 263540
2016-03-15 15:44:57 +08:00
s_ttracedata
// GCN: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]
AMDGPU: Add instruction definitions for VGPR indexing VI added a second method of indexing into VGPRs besides using v_movrel* llvm-svn: 284027
2016-10-13 02:00:51 +08:00
s_set_gpr_idx_off
// VI: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_set_gpr_idx_mode 0
// VI: s_set_gpr_idx_mode 0 ; encoding: [0x00,0x00,0x9d,0xbf]
// NOSICI: error: instruction not supported on this GPU
s_set_gpr_idx_mode 15
// VI: s_set_gpr_idx_mode dst src0 src1 src2 ; encoding: [0x0f,0x00,0x9d,0xbf]
// NOSICI: error: instruction not supported on this GPU