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llvm-project/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll

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SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
2013-11-22 07:21:26 +08:00
; RUN: llc < %s -march=x86-64 -mcpu=athlon | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon-tbird | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon-4 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon-xp | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon-mp | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=k8 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=opteron | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon64 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon-fx | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=k8-sse3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=opteron-sse3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=athlon64-sse3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=amdfam10 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=btver1 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=btver2 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=bdver2 | FileCheck %s
[X86] Add 'FeatureSlowSHLD' to cpu 'bdver4' As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing. llvm-svn: 276569
2016-07-25 00:00:53 +08:00
; RUN: llc < %s -march=x86-64 -mcpu=bdver3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=bdver4 | FileCheck %s
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
2017-01-10 14:01:16 +08:00
; RUN: llc < %s -march=x86-64 -mcpu=znver1 | FileCheck %s
SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
2013-11-22 07:21:26 +08:00
; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
; instructions.
;uint64_t lshift(uint64_t a, uint64_t b, int c)
;{
; return (a << c) | (b >> (64-c));
;}
define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
entry:
; CHECK-NOT: shld
%sh_prom = zext i32 %c to i64
%shl = shl i64 %a, %sh_prom
%sub = sub nsw i32 64, %c
%sh_prom1 = zext i32 %sub to i64
%shr = lshr i64 %b, %sh_prom1
%or = or i64 %shr, %shl
ret i64 %or
}
;uint64_t rshift(uint64_t a, uint64_t b, int c)
;{
; return (a >> c) | (b << (64-c));
;}
define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
entry:
; CHECK-NOT: shrd
%sh_prom = zext i32 %c to i64
%shr = lshr i64 %a, %sh_prom
%sub = sub nsw i32 64, %c
%sh_prom1 = zext i32 %sub to i64
%shl = shl i64 %b, %sh_prom1
%or = or i64 %shl, %shr
ret i64 %or
}