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llvm-project/llvm/test/CodeGen/ARM/intrinsics-v8.ll

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[ARMv8] Implement the new DMB/DSB operands. This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
2013-09-05 23:35:24 +08:00
; RUN: llc < %s -mtriple=armv8 -mattr=+db | FileCheck %s
define void @test() {
; CHECK: dmb sy
call void @llvm.arm.dmb(i32 15)
; CHECK: dmb osh
call void @llvm.arm.dmb(i32 3)
; CHECK: dsb sy
call void @llvm.arm.dsb(i32 15)
; CHECK: dsb ishld
call void @llvm.arm.dsb(i32 9)
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
2013-10-01 20:39:11 +08:00
; CHECK: sevl
ARM: remove @llvm.arm.sevl This intrinsic is no longer needed with the new @llvm.arm.hint(i32) intrinsic which provides a generic, extensible manner for adding hint instructions. This functionality can now be represented as @llvm.arm.hint(i32 5). llvm-svn: 207246
2014-04-26 01:51:25 +08:00
tail call void @llvm.arm.hint(i32 5) nounwind
[ARMv8] Implement the new DMB/DSB operands. This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
2013-09-05 23:35:24 +08:00
ret void
}
declare void @llvm.arm.dmb(i32)
declare void @llvm.arm.dsb(i32)
ARM: remove @llvm.arm.sevl This intrinsic is no longer needed with the new @llvm.arm.hint(i32) intrinsic which provides a generic, extensible manner for adding hint instructions. This functionality can now be represented as @llvm.arm.hint(i32 5). llvm-svn: 207246
2014-04-26 01:51:25 +08:00
declare void @llvm.arm.hint(i32) nounwind