2014-05-30 18:09:59 +08:00
|
|
|
; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic -mcpu=arm1136jf-s -arm-atomic-cfg-tidy=0 | FileCheck %s
|
2011-02-09 01:41:12 +08:00
|
|
|
; rdar://8959122 illegal register operands for UMULL instruction
|
|
|
|
|
; in cfrac nightly test.
|
|
|
|
|
; Armv6 generates a umull that must write to two distinct destination regs.
|
|
|
|
|
|
|
|
|
|
; ModuleID = 'bugpoint-reduced-simplified.bc'
|
|
|
|
|
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
|
|
|
|
|
target triple = "armv6-apple-darwin10"
|
|
|
|
|
|
2014-05-30 16:59:55 +08:00
|
|
|
define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
|
2011-02-09 01:41:12 +08:00
|
|
|
entry:
|
|
|
|
|
br i1 false, label %bb3, label %bb
|
|
|
|
|
|
|
|
|
|
bb: ; preds = %entry
|
|
|
|
|
br label %bb3
|
|
|
|
|
|
|
|
|
|
bb3: ; preds = %bb, %entry
|
|
|
|
|
%0 = call noalias i8* @malloc() nounwind
|
2014-05-30 16:59:55 +08:00
|
|
|
br i1 %tst, label %bb46, label %bb8
|
2011-02-09 01:41:12 +08:00
|
|
|
|
|
|
|
|
bb8: ; preds = %bb3
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%1 = getelementptr inbounds i8, i8* %0, i32 0
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 0, i8* %1, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
%2 = call i32 @ptou() nounwind
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%3 = udiv i32 %2, 10
|
|
|
|
|
%4 = urem i32 %3, 10
|
|
|
|
|
%5 = icmp ult i32 %4, 10
|
|
|
|
|
%6 = trunc i32 %4 to i8
|
|
|
|
|
%7 = or i8 %6, 48
|
|
|
|
|
%8 = add i8 %6, 87
|
|
|
|
|
%iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.1, i8* %p8, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%9 = udiv i32 %2, 100
|
|
|
|
|
%10 = urem i32 %9, 10
|
|
|
|
|
%11 = icmp ult i32 %10, 10
|
|
|
|
|
%12 = trunc i32 %10 to i8
|
|
|
|
|
%13 = or i8 %12, 48
|
|
|
|
|
%14 = add i8 %12, 87
|
|
|
|
|
%iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.2, i8* %p8, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%15 = udiv i32 %2, 10000
|
|
|
|
|
%16 = urem i32 %15, 10
|
|
|
|
|
%17 = icmp ult i32 %16, 10
|
|
|
|
|
%18 = trunc i32 %16 to i8
|
|
|
|
|
%19 = or i8 %18, 48
|
|
|
|
|
%20 = add i8 %18, 87
|
|
|
|
|
%iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.4, i8* null, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%21 = udiv i32 %2, 100000
|
|
|
|
|
%22 = urem i32 %21, 10
|
|
|
|
|
%23 = icmp ult i32 %22, 10
|
2014-05-30 16:59:55 +08:00
|
|
|
%iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.5, i8* %p8, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%24 = udiv i32 %2, 1000000
|
|
|
|
|
%25 = urem i32 %24, 10
|
|
|
|
|
%26 = icmp ult i32 %25, 10
|
|
|
|
|
%27 = trunc i32 %25 to i8
|
|
|
|
|
%28 = or i8 %27, 48
|
|
|
|
|
%29 = add i8 %27, 87
|
|
|
|
|
%iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.6, i8* %p8, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%30 = udiv i32 %2, 10000000
|
|
|
|
|
%31 = urem i32 %30, 10
|
|
|
|
|
%32 = icmp ult i32 %31, 10
|
|
|
|
|
%33 = trunc i32 %31 to i8
|
|
|
|
|
%34 = or i8 %33, 48
|
|
|
|
|
%35 = add i8 %33, 87
|
|
|
|
|
%iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.7, i8* %p8, align 1
|
2011-02-09 01:41:12 +08:00
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
; CHECK: umull [[REGISTER:lr|r[0-9]+]],
|
|
|
|
|
; CHECK-NOT: [[REGISTER]],
|
|
|
|
|
; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
|
|
|
|
|
%36 = udiv i32 %2, 100000000
|
|
|
|
|
%37 = urem i32 %36, 10
|
|
|
|
|
%38 = icmp ult i32 %37, 10
|
|
|
|
|
%39 = trunc i32 %37 to i8
|
|
|
|
|
%40 = or i8 %39, 48
|
|
|
|
|
%41 = add i8 %39, 87
|
|
|
|
|
%iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
store volatile i8 %iftmp.5.0.8, i8* null, align 1
|
2014-05-30 16:59:55 +08:00
|
|
|
br label %bb46
|
2011-02-09 01:41:12 +08:00
|
|
|
|
|
|
|
|
bb46: ; preds = %bb3
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declare noalias i8* @malloc() nounwind
|
|
|
|
|
|
|
|
|
|
declare i32 @ptou()
|