2010-06-09 00:52:24 +08:00
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//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2010-06-09 00:52:24 +08:00
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//
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//===----------------------------------------------------------------------===//
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2017-11-14 00:16:33 +08:00
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#include "lldb/Utility/ArchSpec.h"
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2010-06-09 00:52:24 +08:00
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2018-05-01 08:05:54 +08:00
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#include "lldb/Utility/Log.h"
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2017-03-22 02:25:04 +08:00
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#include "lldb/Utility/StringList.h"
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2018-11-12 07:16:43 +08:00
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#include "lldb/lldb-defines.h"
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2017-04-07 05:28:29 +08:00
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#include "llvm/ADT/STLExtras.h"
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2017-06-07 11:48:56 +08:00
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#include "llvm/BinaryFormat/COFF.h"
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#include "llvm/BinaryFormat/ELF.h"
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2018-11-12 07:16:43 +08:00
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#include "llvm/BinaryFormat/MachO.h"
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#include "llvm/Support/Compiler.h"
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2017-04-07 05:28:29 +08:00
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2010-06-09 00:52:24 +08:00
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using namespace lldb;
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using namespace lldb_private;
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2012-11-04 11:20:05 +08:00
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static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
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bool try_inverse, bool enforce_exact_match);
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2011-02-23 08:35:02 +08:00
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namespace lldb_private {
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2010-06-09 00:52:24 +08:00
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2011-02-23 08:35:02 +08:00
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struct CoreDefinition {
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ByteOrder default_byte_order;
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uint32_t addr_byte_size;
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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uint32_t min_opcode_byte_size;
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uint32_t max_opcode_byte_size;
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2011-02-23 08:35:02 +08:00
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llvm::Triple::ArchType machine;
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ArchSpec::Core core;
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2014-07-24 02:12:06 +08:00
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const char *const name;
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2011-02-23 08:35:02 +08:00
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};
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2010-06-09 00:52:24 +08:00
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2016-03-02 09:09:03 +08:00
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} // namespace lldb_private
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2010-06-11 11:25:34 +08:00
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2011-02-23 08:35:02 +08:00
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// This core information can be looked using the ArchSpec::Core as the index
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2014-07-24 02:12:06 +08:00
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static const CoreDefinition g_core_definitions[] = {
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
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"arm"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
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"armv4"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
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"armv4t"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
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"armv5"},
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2011-12-17 02:15:52 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
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"armv5e"},
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
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"armv5t"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
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"armv6"},
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2013-09-28 07:21:54 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
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"armv6m"},
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
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"armv7"},
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2019-11-13 08:30:25 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
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"armv7l"},
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
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"armv7f"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
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"armv7s"},
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2013-03-08 09:20:17 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
|
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"armv7k"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
|
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"armv7m"},
|
|
|
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
|
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"armv7em"},
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
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|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
|
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"xscale"},
|
2011-12-17 02:15:52 +08:00
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
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"thumb"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
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"thumbv4t"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
|
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"thumbv5"},
|
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
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"thumbv5e"},
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{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
|
|
|
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"thumbv6"},
|
2013-09-28 07:21:54 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
|
|
|
|
"thumbv6m"},
|
2011-12-17 02:15:52 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
|
|
|
|
"thumbv7"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
|
|
|
|
"thumbv7f"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
|
|
|
|
"thumbv7s"},
|
2013-03-08 09:20:17 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
|
|
|
|
"thumbv7k"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
|
|
|
|
"thumbv7m"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
|
|
|
|
"thumbv7em"},
|
2014-07-23 22:37:35 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
|
|
|
|
ArchSpec::eCore_arm_arm64, "arm64"},
|
2014-08-28 22:32:43 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
|
|
|
|
ArchSpec::eCore_arm_armv8, "armv8"},
|
2019-11-13 08:30:25 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
|
[LLDB] Add ObjectFileWasm plugin for WebAssembly debugging
Summary:
This is the first in a series of patches to enable LLDB debugging of
WebAssembly targets.
Current versions of Clang emit (partial) DWARF debug information in WebAssembly
modules and we can leverage this debug information to give LLDB the ability to
do source-level debugging of Wasm code that runs in a WebAssembly engine.
A way to do this could be to use the remote debugging functionalities provided
by LLDB via the GDB-remote protocol. Remote debugging can indeed be useful not
only to connect a debugger to a process running on a remote machine, but also to
connect the debugger to a managed VM or script engine that runs locally,
provided that the engine implements a GDB-remote stub that offers the ability to
access the engine runtime internal state.
To make this work, the GDB-remote protocol would need to be extended with a few
Wasm-specific custom query commands, used to access aspects of the Wasm engine
state (like the Wasm memory, Wasm local and global variables, and so on).
Furthermore, the DWARF format would need to be enriched with a few Wasm-specific
extensions, here detailed: https://yurydelendik.github.io/webassembly-dwarf.
This CL introduce classes **ObjectFileWasm**, a file plugin to represent a Wasm
module loaded in a debuggee process. It knows how to parse Wasm modules and
store the Code section and the DWARF-specific sections.
Reviewers: jasonmolenda, clayborg, labath
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D71575
2020-01-16 07:29:24 +08:00
|
|
|
ArchSpec::eCore_arm_armv8l, "armv8l"},
|
2019-10-17 03:14:49 +08:00
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
|
[LLDB] Add ObjectFileWasm plugin for WebAssembly debugging
Summary:
This is the first in a series of patches to enable LLDB debugging of
WebAssembly targets.
Current versions of Clang emit (partial) DWARF debug information in WebAssembly
modules and we can leverage this debug information to give LLDB the ability to
do source-level debugging of Wasm code that runs in a WebAssembly engine.
A way to do this could be to use the remote debugging functionalities provided
by LLDB via the GDB-remote protocol. Remote debugging can indeed be useful not
only to connect a debugger to a process running on a remote machine, but also to
connect the debugger to a managed VM or script engine that runs locally,
provided that the engine implements a GDB-remote stub that offers the ability to
access the engine runtime internal state.
To make this work, the GDB-remote protocol would need to be extended with a few
Wasm-specific custom query commands, used to access aspects of the Wasm engine
state (like the Wasm memory, Wasm local and global variables, and so on).
Furthermore, the DWARF format would need to be enriched with a few Wasm-specific
extensions, here detailed: https://yurydelendik.github.io/webassembly-dwarf.
This CL introduce classes **ObjectFileWasm**, a file plugin to represent a Wasm
module loaded in a debuggee process. It knows how to parse Wasm modules and
store the Code section and the DWARF-specific sections.
Reviewers: jasonmolenda, clayborg, labath
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D71575
2020-01-16 07:29:24 +08:00
|
|
|
ArchSpec::eCore_arm_arm64_32, "arm64_32"},
|
2014-08-28 22:32:43 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
|
|
|
|
ArchSpec::eCore_arm_aarch64, "aarch64"},
|
2013-10-10 08:59:47 +08:00
|
|
|
|
2015-04-23 14:36:20 +08:00
|
|
|
// mips32, mips32r2, mips32r3, mips32r5, mips32r6
|
2015-07-16 11:51:55 +08:00
|
|
|
{eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
|
|
|
|
"mips"},
|
|
|
|
{eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
|
|
|
|
"mipsr2"},
|
|
|
|
{eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
|
|
|
|
"mipsr3"},
|
|
|
|
{eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
|
|
|
|
"mipsr5"},
|
|
|
|
{eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
|
|
|
|
"mipsr6"},
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
|
|
|
|
"mipsel"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
|
2011-04-14 06:47:15 +08:00
|
|
|
ArchSpec::eCore_mips32r2el, "mipsr2el"},
|
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
|
2014-04-08 22:48:48 +08:00
|
|
|
ArchSpec::eCore_mips32r3el, "mipsr3el"},
|
2014-02-19 19:16:46 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
|
|
|
|
ArchSpec::eCore_mips32r5el, "mipsr5el"},
|
2012-09-20 06:25:17 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
|
2014-08-27 20:09:39 +08:00
|
|
|
ArchSpec::eCore_mips32r6el, "mipsr6el"},
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2015-04-23 14:36:20 +08:00
|
|
|
// mips64, mips64r2, mips64r3, mips64r5, mips64r6
|
2014-07-24 02:12:06 +08:00
|
|
|
{eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
|
2015-07-16 11:51:55 +08:00
|
|
|
"mips64"},
|
|
|
|
{eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
|
|
|
|
"mips64r2"},
|
|
|
|
{eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
|
|
|
|
"mips64r3"},
|
|
|
|
{eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
|
|
|
|
"mips64r5"},
|
|
|
|
{eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
|
|
|
|
"mips64r6"},
|
2014-07-24 02:12:06 +08:00
|
|
|
{eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
|
2015-07-16 11:51:55 +08:00
|
|
|
ArchSpec::eCore_mips64el, "mips64el"},
|
|
|
|
{eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
|
|
|
|
ArchSpec::eCore_mips64r2el, "mips64r2el"},
|
|
|
|
{eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
|
|
|
|
ArchSpec::eCore_mips64r3el, "mips64r3el"},
|
|
|
|
{eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
|
|
|
|
ArchSpec::eCore_mips64r5el, "mips64r5el"},
|
|
|
|
{eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
|
2015-04-23 14:36:20 +08:00
|
|
|
ArchSpec::eCore_mips64r6el, "mips64r6el"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-07-24 02:12:06 +08:00
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
|
2014-10-31 10:34:28 +08:00
|
|
|
"powerpc"},
|
2013-08-13 02:34:04 +08:00
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
|
|
|
|
"ppc601"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
|
|
|
|
"ppc602"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
|
|
|
|
"ppc603"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
|
|
|
|
"ppc603e"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
|
|
|
|
"ppc603ev"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
|
|
|
|
"ppc604"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
|
|
|
|
"ppc604e"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
|
|
|
|
"ppc620"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
|
|
|
|
"ppc750"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
|
|
|
|
"ppc7400"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
|
|
|
|
"ppc7450"},
|
|
|
|
{eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
|
|
|
|
"ppc970"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
Now a ppc64le binary is correctly detected:
(lldb) target create "tst"
Current executable set to 'tst' (powerpc64le).
(lldb) disassemble -n main
tst`main:
tst[0x7b0] <+0>: addis 2, 12, 2
tst[0x7b4] <+4>: addi 2, 2, 30544
tst[0x7b8] <+8>: mflr 0
Wihout the patch, the endianess was incorrect:
(lldb) target create "tst"
Current executable set to 'tst' (powerpc64).
(lldb) disassemble -n main
tst`main:
tst[0x7b0] <+0>: .long 0x02004c3c ; unknown opcode
tst[0x7b4] <+4>: rlwimi 23, 3, 8, 8, 28
tst[0x7b8] <+8>: lhzu 16, 2172(2)
tst[0x7bc] <+12>: .long 0x100001f8 ; unknown opcode
Simple binary used is identified as:
$ file tst
tst: ELF 64-bit LSB shared object, 64-bit PowerPC or cisco 7500, version
1 (SYSV), dynamically linked, interpreter /lib64/ld64.so.2, for
GNU/Linux 3.2.0, BuildID[sha1]=17a8fa2b24ce2837ba6625fabb34e6b29c6c5db7,
not stripped
Patch by Gustavo Serra Scalet <gustavo.scalet@eldorado.org.br>
Differential Revision: https://reviews.llvm.org/D36804
llvm-svn: 312151
2017-08-31 02:36:48 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
|
2017-11-14 00:16:33 +08:00
|
|
|
ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
|
2014-07-24 02:12:06 +08:00
|
|
|
{eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
|
2014-10-31 10:34:28 +08:00
|
|
|
"powerpc64"},
|
2013-08-13 02:34:04 +08:00
|
|
|
{eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
|
|
|
|
ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2016-04-14 22:28:34 +08:00
|
|
|
{eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
|
|
|
|
ArchSpec::eCore_s390x_generic, "s390x"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-02-19 19:16:46 +08:00
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
ArchSpec::eCore_sparc_generic, "sparc"},
|
2014-07-02 07:33:32 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
ArchSpec::eCore_sparc9_generic, "sparcv9"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2011-04-14 06:47:15 +08:00
|
|
|
{eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
|
2016-09-07 04:57:50 +08:00
|
|
|
"i386"},
|
2011-04-14 06:47:15 +08:00
|
|
|
{eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
|
2016-09-07 04:57:50 +08:00
|
|
|
"i486"},
|
2011-04-14 06:47:15 +08:00
|
|
|
{eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
|
|
|
|
ArchSpec::eCore_x86_32_i486sx, "i486sx"},
|
|
|
|
{eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
|
2016-09-07 04:57:50 +08:00
|
|
|
"i686"},
|
|
|
|
|
2014-01-23 07:42:03 +08:00
|
|
|
{eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
|
2012-09-20 06:25:17 +08:00
|
|
|
ArchSpec::eCore_x86_64_x86_64, "x86_64"},
|
2014-01-23 07:42:03 +08:00
|
|
|
{eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
|
|
|
|
ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
|
2014-02-19 19:16:46 +08:00
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
|
|
|
|
ArchSpec::eCore_hexagon_generic, "hexagon"},
|
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
|
|
|
|
ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
|
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
|
|
|
|
ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-07-02 07:33:32 +08:00
|
|
|
{eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
|
2012-09-20 06:25:17 +08:00
|
|
|
ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
|
2014-07-02 07:33:32 +08:00
|
|
|
{eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
|
|
|
|
ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
|
[LLDB] Add ObjectFileWasm plugin for WebAssembly debugging
Summary:
This is the first in a series of patches to enable LLDB debugging of
WebAssembly targets.
Current versions of Clang emit (partial) DWARF debug information in WebAssembly
modules and we can leverage this debug information to give LLDB the ability to
do source-level debugging of Wasm code that runs in a WebAssembly engine.
A way to do this could be to use the remote debugging functionalities provided
by LLDB via the GDB-remote protocol. Remote debugging can indeed be useful not
only to connect a debugger to a process running on a remote machine, but also to
connect the debugger to a managed VM or script engine that runs locally,
provided that the engine implements a GDB-remote stub that offers the ability to
access the engine runtime internal state.
To make this work, the GDB-remote protocol would need to be extended with a few
Wasm-specific custom query commands, used to access aspects of the Wasm engine
state (like the Wasm memory, Wasm local and global variables, and so on).
Furthermore, the DWARF format would need to be enriched with a few Wasm-specific
extensions, here detailed: https://yurydelendik.github.io/webassembly-dwarf.
This CL introduce classes **ObjectFileWasm**, a file plugin to represent a Wasm
module loaded in a debuggee process. It knows how to parse Wasm modules and
store the Code section and the DWARF-specific sections.
Reviewers: jasonmolenda, clayborg, labath
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D71575
2020-01-16 07:29:24 +08:00
|
|
|
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
|
|
|
|
|
|
|
|
{eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
|
|
|
|
"wasm32"},
|
2019-03-28 00:23:50 +08:00
|
|
|
};
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-07-24 02:12:06 +08:00
|
|
|
// Ensure that we have an entry in the g_core_definitions for each core. If you
|
2018-05-01 00:49:04 +08:00
|
|
|
// comment out an entry above, you will need to comment out the corresponding
|
|
|
|
// ArchSpec::Core enumeration.
|
2014-07-29 00:44:28 +08:00
|
|
|
static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
|
|
|
|
ArchSpec::kNumCores,
|
|
|
|
"make sure we have one core definition for each core");
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
struct ArchDefinitionEntry {
|
|
|
|
ArchSpec::Core core;
|
|
|
|
uint32_t cpu;
|
|
|
|
uint32_t sub;
|
2012-09-20 06:25:17 +08:00
|
|
|
uint32_t cpu_mask;
|
|
|
|
uint32_t sub_mask;
|
2011-02-23 08:35:02 +08:00
|
|
|
};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
struct ArchDefinition {
|
|
|
|
ArchitectureType type;
|
|
|
|
size_t num_entries;
|
|
|
|
const ArchDefinitionEntry *entries;
|
|
|
|
const char *name;
|
2010-06-09 00:52:24 +08:00
|
|
|
};
|
|
|
|
|
2018-07-14 02:28:14 +08:00
|
|
|
void ArchSpec::ListSupportedArchNames(StringList &list) {
|
|
|
|
for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
|
|
|
|
list.AppendString(g_core_definitions[i].name);
|
|
|
|
}
|
|
|
|
|
[lldb][NFC] Remove WordComplete mode, make result array indexed from 0 and remove any undocumented/redundant return values
Summary:
We still have some leftovers of the old completion API in the internals of
LLDB that haven't been replaced by the new CompletionRequest. These leftovers
are:
* The return values (int/size_t) in all completion functions.
* Our result array that starts indexing at 1.
* `WordComplete` mode.
I didn't replace them back then because it's tricky to figure out what exactly they
are used for and the completion code is relatively untested. I finally got around
to writing more tests for the API and understanding the semantics, so I think it's
a good time to get rid of them.
A few words why those things should be removed/replaced:
* The return values are really cryptic, partly redundant and rarely documented.
They are also completely ignored by Xcode, so whatever information they contain will end up
breaking Xcode's completion mechanism. They are also partly impossible to even implement
as we assign negative values special meaning and our completion API sometimes returns size_t.
Completion functions are supposed to return -2 to rewrite the current line. We seem to use this
in some untested code path to expand the history repeat character to the full command, but
I haven't figured out why that doesn't work at the moment.
Completion functions return -1 to 'insert the completion character', but that isn't implemented
(even though we seem to activate this feature in LLDB sometimes).
All positive values have to match the number of results. This is obviously just redundant information
as the user can just look at the result list to get that information (which is what Xcode does).
* The result array that starts indexing at 1 is obviously unexpected. The first element of the array is
reserved for the common prefix of all completions (e.g. "foobar" and "footar" -> "foo"). The idea is
that we calculate this to make the life of the API caller easier, but obviously forcing people to have
1-based indices is not helpful (or even worse, forces them to manually copy the results to make it
0-based like Xcode has to do).
* The `WordComplete` mode indicates that LLDB should enter a space behind the completion. The
idea is that we let the top-level API know that we just provided a full completion. Interestingly we
`WordComplete` is just a single bool that somehow represents all N completions. And we always
provide full completions in LLDB, so in theory it should always be true.
The only use it currently serves is providing redundant information about whether we have a single
definitive completion or not (which we already know from the number of results we get).
This patch essentially removes `WordComplete` mode and makes the result array indexed from 0.
It also removes all return values from all internal completion functions. The only non-redundant information
they contain is about rewriting the current line (which is broken), so that functionality was moved
to the CompletionRequest API. So you can now do `addCompletion("blub", "description", CompletionMode::RewriteLine)`
to do the same.
For the SB API we emulate the old behaviour by making the array indexed from 1 again with the common
prefix at index 0. I didn't keep the special negative return codes as we either never sent them before (e.g. -2) or we
didn't even implement them in the Editline handler (e.g. -1).
I tried to keep this patch minimal and I'm aware we can probably now even further simplify a bunch of related code,
but I would prefer doing this in follow-up NFC commits
Reviewers: JDevlieghere
Reviewed By: JDevlieghere
Subscribers: arphaman, abidh, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D66536
llvm-svn: 369624
2019-08-22 15:41:23 +08:00
|
|
|
void ArchSpec::AutoComplete(CompletionRequest &request) {
|
2019-09-23 16:59:21 +08:00
|
|
|
for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
|
|
|
|
request.TryCompleteCurrentArg(g_core_definitions[i].name);
|
2011-04-14 06:47:15 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
#define CPU_ANY (UINT32_MAX)
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// A table that gets searched linearly for matches. This table is used to
|
|
|
|
// convert cpu type and subtypes to architecture names, and to convert
|
|
|
|
// architecture names to cpu types and subtypes. The ordering is important and
|
|
|
|
// allows the precedence to be set when the table is built.
|
2012-09-20 06:25:17 +08:00
|
|
|
#define SUBTYPE_MASK 0x00FFFFFFu
|
2016-03-02 09:09:03 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinitionEntry g_macho_arch_entries[] = {
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY,
|
|
|
|
UINT32_MAX, UINT32_MAX},
|
|
|
|
{ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2013-10-08 11:01:08 +08:00
|
|
|
{ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2014-03-30 02:54:20 +08:00
|
|
|
{ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2014-11-12 09:11:36 +08:00
|
|
|
{ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2014-03-30 02:54:20 +08:00
|
|
|
{ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2019-10-17 03:14:49 +08:00
|
|
|
{ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
2014-11-12 09:11:36 +08:00
|
|
|
{ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2013-10-08 11:01:08 +08:00
|
|
|
{ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY,
|
|
|
|
UINT32_MAX, UINT32_MAX},
|
|
|
|
{ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
Add float/vector registers for ppc64le
Summary: Add read and write functions for VSX, VMX and float registers and fix watchpoint size
Reviewers: clayborg
Reviewed By: clayborg
Subscribers: eugene, labath, clayborg, nemanjai, kbarton, JDevlieghere, anajuliapc, gut, lbianc, lldb-commits
Differential Revision: https://reviews.llvm.org/D39487
Patch by: Alexandre Yukio Yamashita <alexandre.yamashita@eldorado.org.br>
llvm-svn: 317329
2017-11-03 23:22:36 +08:00
|
|
|
{ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84,
|
2014-01-23 07:42:03 +08:00
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY,
|
|
|
|
UINT32_MAX, UINT32_MAX},
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX,
|
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX,
|
2014-01-23 07:42:03 +08:00
|
|
|
SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8,
|
|
|
|
UINT32_MAX, SUBTYPE_MASK},
|
|
|
|
{ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY,
|
|
|
|
UINT32_MAX, UINT32_MAX},
|
2012-09-20 06:25:17 +08:00
|
|
|
// Catch any unknown mach architectures so we can always use the object and
|
|
|
|
// symbol mach-o files
|
2013-08-27 13:04:57 +08:00
|
|
|
{ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
|
|
|
|
{ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u,
|
|
|
|
0x00000000u}};
|
2016-03-02 09:09:03 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinition g_macho_arch_def = {
|
2014-06-27 13:17:41 +08:00
|
|
|
eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries),
|
2011-02-23 08:35:02 +08:00
|
|
|
g_macho_arch_entries, "mach-o"};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// A table that gets searched linearly for matches. This table is used to
|
|
|
|
// convert cpu type and subtypes to architecture names, and to convert
|
|
|
|
// architecture names to cpu types and subtypes. The ordering is important and
|
|
|
|
// allows the precedence to be set when the table is built.
|
|
|
|
static const ArchDefinitionEntry g_elf_arch_entries[] = {
|
2012-09-20 06:25:17 +08:00
|
|
|
{ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
|
|
|
|
{ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
|
2015-06-20 01:02:25 +08:00
|
|
|
{ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
|
2012-09-20 06:25:17 +08:00
|
|
|
{ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
|
Now a ppc64le binary is correctly detected:
(lldb) target create "tst"
Current executable set to 'tst' (powerpc64le).
(lldb) disassemble -n main
tst`main:
tst[0x7b0] <+0>: addis 2, 12, 2
tst[0x7b4] <+4>: addi 2, 2, 30544
tst[0x7b8] <+8>: mflr 0
Wihout the patch, the endianess was incorrect:
(lldb) target create "tst"
Current executable set to 'tst' (powerpc64).
(lldb) disassemble -n main
tst`main:
tst[0x7b0] <+0>: .long 0x02004c3c ; unknown opcode
tst[0x7b4] <+4>: rlwimi 23, 3, 8, 8, 28
tst[0x7b8] <+8>: lhzu 16, 2172(2)
tst[0x7bc] <+12>: .long 0x100001f8 ; unknown opcode
Simple binary used is identified as:
$ file tst
tst: ELF 64-bit LSB shared object, 64-bit PowerPC or cisco 7500, version
1 (SYSV), dynamically linked, interpreter /lib64/ld64.so.2, for
GNU/Linux 3.2.0, BuildID[sha1]=17a8fa2b24ce2837ba6625fabb34e6b29c6c5db7,
not stripped
Patch by Gustavo Serra Scalet <gustavo.scalet@eldorado.org.br>
Differential Revision: https://reviews.llvm.org/D36804
llvm-svn: 312151
2017-08-31 02:36:48 +08:00
|
|
|
{ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
|
2012-09-20 06:25:17 +08:00
|
|
|
{ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
|
|
|
|
{ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
|
2014-08-28 22:32:43 +08:00
|
|
|
{ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
|
2016-04-14 22:28:34 +08:00
|
|
|
{ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
|
2012-09-20 06:25:17 +08:00
|
|
|
{ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
|
2013-10-10 08:59:47 +08:00
|
|
|
{ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
|
2015-04-23 14:36:20 +08:00
|
|
|
{ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
|
|
|
|
{ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
|
|
|
|
{ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
|
|
|
|
{ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
|
|
|
|
{ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
|
|
|
|
{ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
|
|
|
|
{ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
|
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
|
|
|
|
{ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
|
|
|
|
{ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
|
|
|
|
{ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
|
|
|
|
{ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
|
|
|
|
{ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
|
|
|
|
ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
|
2014-07-02 07:33:32 +08:00
|
|
|
{ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
|
2019-10-17 23:16:21 +08:00
|
|
|
{ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
|
2019-12-17 16:13:23 +08:00
|
|
|
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
|
2010-06-11 11:25:34 +08:00
|
|
|
};
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinition g_elf_arch_def = {
|
2017-11-14 00:16:33 +08:00
|
|
|
eArchTypeELF,
|
|
|
|
llvm::array_lengthof(g_elf_arch_entries),
|
|
|
|
g_elf_arch_entries,
|
2011-02-23 08:35:02 +08:00
|
|
|
"elf",
|
|
|
|
};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2013-08-27 13:04:33 +08:00
|
|
|
static const ArchDefinitionEntry g_coff_arch_entries[] = {
|
2014-07-29 00:44:49 +08:00
|
|
|
{ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
|
2013-08-27 13:04:33 +08:00
|
|
|
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
|
|
|
|
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
|
|
|
|
{ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
|
2014-03-11 11:09:08 +08:00
|
|
|
{ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
|
2013-08-27 13:04:33 +08:00
|
|
|
{ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
|
|
|
|
{ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
|
2019-09-24 20:20:52 +08:00
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
|
|
|
|
{ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
|
|
|
|
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
|
2013-08-27 13:04:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const ArchDefinition g_coff_arch_def = {
|
2017-11-14 00:16:33 +08:00
|
|
|
eArchTypeCOFF,
|
|
|
|
llvm::array_lengthof(g_coff_arch_entries),
|
|
|
|
g_coff_arch_entries,
|
|
|
|
"pe-coff",
|
2013-08-27 13:04:33 +08:00
|
|
|
};
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Table of all ArchDefinitions
|
|
|
|
static const ArchDefinition *g_arch_definitions[] = {
|
|
|
|
&g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def};
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2014-06-27 13:17:41 +08:00
|
|
|
static const size_t k_num_arch_definitions =
|
|
|
|
llvm::array_lengthof(g_arch_definitions);
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Static helper functions.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
// Get the architecture definition for a given object type.
|
|
|
|
static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
|
|
|
|
for (unsigned int i = 0; i < k_num_arch_definitions; ++i) {
|
|
|
|
const ArchDefinition *def = g_arch_definitions[i];
|
|
|
|
if (def->type == arch_type)
|
|
|
|
return def;
|
|
|
|
}
|
2016-03-02 09:09:03 +08:00
|
|
|
return nullptr;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
// Get an architecture definition by name.
|
|
|
|
static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
|
2014-07-24 02:12:06 +08:00
|
|
|
for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) {
|
2011-02-23 08:35:02 +08:00
|
|
|
if (name.equals_lower(g_core_definitions[i].name))
|
|
|
|
return &g_core_definitions[i];
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2016-03-02 09:09:03 +08:00
|
|
|
return nullptr;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
|
2017-11-02 07:49:23 +08:00
|
|
|
if (core < llvm::array_lengthof(g_core_definitions))
|
2011-02-23 08:35:02 +08:00
|
|
|
return &g_core_definitions[core];
|
2016-03-02 09:09:03 +08:00
|
|
|
return nullptr;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
// Get a definition entry by cpu type and subtype.
|
|
|
|
static const ArchDefinitionEntry *
|
|
|
|
FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
|
2016-03-02 09:09:03 +08:00
|
|
|
if (def == nullptr)
|
|
|
|
return nullptr;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchDefinitionEntry *entries = def->entries;
|
|
|
|
for (size_t i = 0; i < def->num_entries; ++i) {
|
2012-09-20 06:25:17 +08:00
|
|
|
if (entries[i].cpu == (cpu & entries[i].cpu_mask))
|
|
|
|
if (entries[i].sub == (sub & entries[i].sub_mask))
|
2011-02-23 08:35:02 +08:00
|
|
|
return &entries[i];
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2016-03-02 09:09:03 +08:00
|
|
|
return nullptr;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinitionEntry *
|
|
|
|
FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
|
2016-03-02 09:09:03 +08:00
|
|
|
if (def == nullptr)
|
|
|
|
return nullptr;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchDefinitionEntry *entries = def->entries;
|
|
|
|
for (size_t i = 0; i < def->num_entries; ++i) {
|
|
|
|
if (entries[i].core == core)
|
|
|
|
return &entries[i];
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2016-03-02 09:09:03 +08:00
|
|
|
return nullptr;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Constructors and destructors.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2016-09-16 05:32:57 +08:00
|
|
|
ArchSpec::ArchSpec() {}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2016-09-16 05:32:57 +08:00
|
|
|
ArchSpec::ArchSpec(const char *triple_cstr) {
|
2012-05-08 09:45:38 +08:00
|
|
|
if (triple_cstr)
|
|
|
|
SetTriple(triple_cstr);
|
|
|
|
}
|
|
|
|
|
2016-09-16 05:32:57 +08:00
|
|
|
ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2016-09-16 05:32:57 +08:00
|
|
|
ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
|
|
|
|
|
|
|
|
ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
|
2011-02-23 08:35:02 +08:00
|
|
|
SetArchitecture(arch_type, cpu, subtype);
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2016-03-02 09:09:03 +08:00
|
|
|
ArchSpec::~ArchSpec() = default;
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
void ArchSpec::Clear() {
|
|
|
|
m_triple = llvm::Triple();
|
|
|
|
m_core = kCore_invalid;
|
|
|
|
m_byte_order = eByteOrderInvalid;
|
2014-01-18 11:02:39 +08:00
|
|
|
m_distribution_id.Clear();
|
2015-07-16 11:51:55 +08:00
|
|
|
m_flags = 0;
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Predicates.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
const char *ArchSpec::GetArchitectureName() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def)
|
|
|
|
return core_def->name;
|
|
|
|
return "unknown";
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2019-05-16 16:37:32 +08:00
|
|
|
bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
|
2016-05-11 21:08:29 +08:00
|
|
|
|
2016-10-12 18:21:09 +08:00
|
|
|
std::string ArchSpec::GetTargetABI() const {
|
|
|
|
|
|
|
|
std::string abi;
|
|
|
|
|
|
|
|
if (IsMIPS()) {
|
|
|
|
switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
|
|
|
|
case ArchSpec::eMIPSABI_N64:
|
|
|
|
abi = "n64";
|
|
|
|
return abi;
|
|
|
|
case ArchSpec::eMIPSABI_N32:
|
|
|
|
abi = "n32";
|
|
|
|
return abi;
|
|
|
|
case ArchSpec::eMIPSABI_O32:
|
|
|
|
abi = "o32";
|
|
|
|
return abi;
|
|
|
|
default:
|
|
|
|
return abi;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return abi;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ArchSpec::SetFlags(std::string elf_abi) {
|
|
|
|
|
|
|
|
uint32_t flag = GetFlags();
|
|
|
|
if (IsMIPS()) {
|
|
|
|
if (elf_abi == "n64")
|
|
|
|
flag |= ArchSpec::eMIPSABI_N64;
|
|
|
|
else if (elf_abi == "n32")
|
|
|
|
flag |= ArchSpec::eMIPSABI_N32;
|
|
|
|
else if (elf_abi == "o32")
|
|
|
|
flag |= ArchSpec::eMIPSABI_O32;
|
|
|
|
}
|
|
|
|
SetFlags(flag);
|
|
|
|
}
|
|
|
|
|
2017-03-03 21:35:49 +08:00
|
|
|
std::string ArchSpec::GetClangTargetCPU() const {
|
2016-02-18 19:53:28 +08:00
|
|
|
std::string cpu;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2019-05-16 16:37:32 +08:00
|
|
|
if (IsMIPS()) {
|
2016-02-18 19:53:28 +08:00
|
|
|
switch (m_core) {
|
|
|
|
case ArchSpec::eCore_mips32:
|
|
|
|
case ArchSpec::eCore_mips32el:
|
|
|
|
cpu = "mips32";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips32r2:
|
|
|
|
case ArchSpec::eCore_mips32r2el:
|
|
|
|
cpu = "mips32r2";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips32r3:
|
|
|
|
case ArchSpec::eCore_mips32r3el:
|
|
|
|
cpu = "mips32r3";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips32r5:
|
|
|
|
case ArchSpec::eCore_mips32r5el:
|
|
|
|
cpu = "mips32r5";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips32r6:
|
|
|
|
case ArchSpec::eCore_mips32r6el:
|
|
|
|
cpu = "mips32r6";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips64:
|
|
|
|
case ArchSpec::eCore_mips64el:
|
|
|
|
cpu = "mips64";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips64r2:
|
|
|
|
case ArchSpec::eCore_mips64r2el:
|
|
|
|
cpu = "mips64r2";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips64r3:
|
|
|
|
case ArchSpec::eCore_mips64r3el:
|
|
|
|
cpu = "mips64r3";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips64r5:
|
|
|
|
case ArchSpec::eCore_mips64r5el:
|
|
|
|
cpu = "mips64r5";
|
|
|
|
break;
|
|
|
|
case ArchSpec::eCore_mips64r6:
|
|
|
|
case ArchSpec::eCore_mips64r6el:
|
|
|
|
cpu = "mips64r6";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2016-02-18 19:53:28 +08:00
|
|
|
return cpu;
|
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
uint32_t ArchSpec::GetMachOCPUType() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def) {
|
|
|
|
const ArchDefinitionEntry *arch_def =
|
|
|
|
FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
|
|
|
|
if (arch_def) {
|
|
|
|
return arch_def->cpu;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return LLDB_INVALID_CPUTYPE;
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
uint32_t ArchSpec::GetMachOCPUSubType() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def) {
|
|
|
|
const ArchDefinitionEntry *arch_def =
|
|
|
|
FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
|
|
|
|
if (arch_def) {
|
2011-03-24 12:28:38 +08:00
|
|
|
return arch_def->sub;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return LLDB_INVALID_CPUTYPE;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2014-09-01 17:06:03 +08:00
|
|
|
uint32_t ArchSpec::GetDataByteSize() const {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t ArchSpec::GetCodeByteSize() const {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
llvm::Triple::ArchType ArchSpec::GetMachine() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def)
|
|
|
|
return core_def->machine;
|
|
|
|
|
|
|
|
return llvm::Triple::UnknownArch;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2019-03-07 05:22:25 +08:00
|
|
|
ConstString ArchSpec::GetDistributionId() const {
|
2014-01-18 11:02:39 +08:00
|
|
|
return m_distribution_id;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ArchSpec::SetDistributionId(const char *distribution_id) {
|
|
|
|
m_distribution_id.SetCString(distribution_id);
|
|
|
|
}
|
|
|
|
|
2010-06-09 00:52:24 +08:00
|
|
|
uint32_t ArchSpec::GetAddressByteSize() const {
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def) {
|
2015-09-09 18:32:20 +08:00
|
|
|
if (core_def->machine == llvm::Triple::mips64 ||
|
|
|
|
core_def->machine == llvm::Triple::mips64el) {
|
|
|
|
// For N32/O32 applications Address size is 4 bytes.
|
|
|
|
if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
|
|
|
|
return 4;
|
|
|
|
}
|
|
|
|
return core_def->addr_byte_size;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2010-06-11 11:25:34 +08:00
|
|
|
return 0;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
ByteOrder ArchSpec::GetDefaultEndian() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def)
|
|
|
|
return core_def->default_byte_order;
|
|
|
|
return eByteOrderInvalid;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2015-03-31 18:21:50 +08:00
|
|
|
bool ArchSpec::CharIsSignedByDefault() const {
|
|
|
|
switch (m_triple.getArch()) {
|
|
|
|
default:
|
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-03-31 18:21:50 +08:00
|
|
|
case llvm::Triple::aarch64:
|
2019-10-17 03:14:49 +08:00
|
|
|
case llvm::Triple::aarch64_32:
|
2015-03-31 18:21:50 +08:00
|
|
|
case llvm::Triple::aarch64_be:
|
|
|
|
case llvm::Triple::arm:
|
|
|
|
case llvm::Triple::armeb:
|
|
|
|
case llvm::Triple::thumb:
|
|
|
|
case llvm::Triple::thumbeb:
|
|
|
|
return m_triple.isOSDarwin() || m_triple.isOSWindows();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-03-31 18:21:50 +08:00
|
|
|
case llvm::Triple::ppc:
|
|
|
|
case llvm::Triple::ppc64:
|
|
|
|
return m_triple.isOSDarwin();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-03-31 18:21:50 +08:00
|
|
|
case llvm::Triple::ppc64le:
|
|
|
|
case llvm::Triple::systemz:
|
|
|
|
case llvm::Triple::xcore:
|
2018-09-07 22:45:32 +08:00
|
|
|
case llvm::Triple::arc:
|
2015-03-31 18:21:50 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
lldb::ByteOrder ArchSpec::GetByteOrder() const {
|
|
|
|
if (m_byte_order == eByteOrderInvalid)
|
|
|
|
return GetDefaultEndian();
|
|
|
|
return m_byte_order;
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mutators.
|
|
|
|
|
|
|
|
bool ArchSpec::SetTriple(const llvm::Triple &triple) {
|
|
|
|
m_triple = triple;
|
2017-04-20 20:30:18 +08:00
|
|
|
UpdateCore();
|
2011-02-23 08:35:02 +08:00
|
|
|
return IsValid();
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2016-10-12 18:21:09 +08:00
|
|
|
bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
|
|
|
|
ArchSpec &arch) {
|
2012-09-20 06:25:17 +08:00
|
|
|
// Accept "12-10" or "12.10" as cpu type/subtype
|
2016-09-16 02:41:48 +08:00
|
|
|
if (triple_str.empty())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
size_t pos = triple_str.find_first_of("-.");
|
|
|
|
if (pos == llvm::StringRef::npos)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
llvm::StringRef cpu_str = triple_str.substr(0, pos);
|
|
|
|
llvm::StringRef remainder = triple_str.substr(pos + 1);
|
|
|
|
if (cpu_str.empty() || remainder.empty())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
llvm::StringRef sub_str;
|
|
|
|
llvm::StringRef vendor;
|
|
|
|
llvm::StringRef os;
|
|
|
|
std::tie(sub_str, remainder) = remainder.split('-');
|
|
|
|
std::tie(vendor, os) = remainder.split('-');
|
|
|
|
|
|
|
|
uint32_t cpu = 0;
|
|
|
|
uint32_t sub = 0;
|
|
|
|
if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
|
|
|
|
return false;
|
|
|
|
if (!vendor.empty() && !os.empty()) {
|
|
|
|
arch.GetTriple().setVendorName(vendor);
|
|
|
|
arch.GetTriple().setOSName(os);
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2016-09-16 02:41:48 +08:00
|
|
|
|
|
|
|
return true;
|
2012-09-20 06:25:17 +08:00
|
|
|
}
|
2016-03-02 09:09:03 +08:00
|
|
|
|
2016-09-16 05:32:57 +08:00
|
|
|
bool ArchSpec::SetTriple(llvm::StringRef triple) {
|
|
|
|
if (triple.empty()) {
|
2012-05-08 09:45:38 +08:00
|
|
|
Clear();
|
2016-09-16 05:32:57 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ParseMachCPUDashSubtypeTriple(triple, *this))
|
|
|
|
return true;
|
|
|
|
|
2017-11-13 23:57:20 +08:00
|
|
|
SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
|
2012-05-08 09:45:38 +08:00
|
|
|
return IsValid();
|
|
|
|
}
|
|
|
|
|
2017-10-31 18:56:03 +08:00
|
|
|
bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
|
|
|
|
return !normalized_triple.getArchName().empty() &&
|
|
|
|
normalized_triple.getOSName().empty() &&
|
|
|
|
normalized_triple.getVendorName().empty() &&
|
|
|
|
normalized_triple.getEnvironmentName().empty();
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2015-01-23 02:59:05 +08:00
|
|
|
void ArchSpec::MergeFrom(const ArchSpec &other) {
|
2019-02-27 07:50:19 +08:00
|
|
|
if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
|
2015-01-23 02:59:05 +08:00
|
|
|
GetTriple().setVendor(other.GetTriple().getVendor());
|
2019-05-09 06:03:22 +08:00
|
|
|
if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
|
2015-01-23 02:59:05 +08:00
|
|
|
GetTriple().setOS(other.GetTriple().getOS());
|
2017-04-20 20:30:18 +08:00
|
|
|
if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
|
2015-01-23 02:59:05 +08:00
|
|
|
GetTriple().setArch(other.GetTriple().getArch());
|
2018-01-05 10:50:24 +08:00
|
|
|
|
2018-05-01 00:49:04 +08:00
|
|
|
// MachO unknown64 isn't really invalid as the debugger can still obtain
|
|
|
|
// information from the binary, e.g. line tables. As such, we don't update
|
|
|
|
// the core here.
|
2018-01-05 10:50:24 +08:00
|
|
|
if (other.GetCore() != eCore_uknownMach64)
|
|
|
|
UpdateCore();
|
2017-04-20 20:30:18 +08:00
|
|
|
}
|
2019-02-27 07:50:19 +08:00
|
|
|
if (!TripleEnvironmentWasSpecified() &&
|
2019-02-27 08:47:39 +08:00
|
|
|
other.TripleEnvironmentWasSpecified()) {
|
|
|
|
GetTriple().setEnvironment(other.GetTriple().getEnvironment());
|
2015-11-06 09:43:36 +08:00
|
|
|
}
|
2016-04-05 13:01:30 +08:00
|
|
|
// If this and other are both arm ArchSpecs and this ArchSpec is a generic
|
2018-05-01 00:49:04 +08:00
|
|
|
// "some kind of arm" spec but the other ArchSpec is a specific arm core,
|
|
|
|
// adopt the specific arm core.
|
2016-04-05 13:01:30 +08:00
|
|
|
if (GetTriple().getArch() == llvm::Triple::arm &&
|
|
|
|
other.GetTriple().getArch() == llvm::Triple::arm &&
|
|
|
|
IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
|
|
|
|
other.GetCore() != ArchSpec::eCore_arm_generic) {
|
|
|
|
m_core = other.GetCore();
|
2019-12-05 16:04:04 +08:00
|
|
|
CoreUpdated(false);
|
2016-04-05 13:01:30 +08:00
|
|
|
}
|
2017-11-05 02:25:51 +08:00
|
|
|
if (GetFlags() == 0) {
|
|
|
|
SetFlags(other.GetFlags());
|
|
|
|
}
|
2015-01-23 02:59:05 +08:00
|
|
|
}
|
|
|
|
|
2015-06-05 21:03:08 +08:00
|
|
|
bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
|
|
|
|
uint32_t sub, uint32_t os) {
|
2011-02-23 08:35:02 +08:00
|
|
|
m_core = kCore_invalid;
|
|
|
|
bool update_triple = true;
|
|
|
|
const ArchDefinition *arch_def = FindArchDefinition(arch_type);
|
|
|
|
if (arch_def) {
|
|
|
|
const ArchDefinitionEntry *arch_def_entry =
|
|
|
|
FindArchDefinitionEntry(arch_def, cpu, sub);
|
|
|
|
if (arch_def_entry) {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
|
|
|
|
if (core_def) {
|
|
|
|
m_core = core_def->core;
|
|
|
|
update_triple = false;
|
2018-05-01 00:49:04 +08:00
|
|
|
// Always use the architecture name because it might be more
|
|
|
|
// descriptive than the architecture enum ("armv7" ->
|
|
|
|
// llvm::Triple::arm).
|
2011-09-21 11:57:31 +08:00
|
|
|
m_triple.setArchName(llvm::StringRef(core_def->name));
|
2011-02-23 08:35:02 +08:00
|
|
|
if (arch_type == eArchTypeMachO) {
|
|
|
|
m_triple.setVendor(llvm::Triple::Apple);
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
// Don't set the OS. It could be simulator, macosx, ios, watchos,
|
2019-03-28 00:23:50 +08:00
|
|
|
// tvos, bridgeos. We could get close with the cpu type - but we
|
|
|
|
// can't get it right all of the time. Better to leave this unset
|
|
|
|
// so other sections of code will set it when they have more
|
|
|
|
// information. NB: don't call m_triple.setOS
|
|
|
|
// (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
|
|
|
|
// the ArchSpec::TripleVendorWasSpecified() method says that any
|
|
|
|
// OSName setting means it was specified.
|
2015-06-05 21:03:08 +08:00
|
|
|
} else if (arch_type == eArchTypeELF) {
|
|
|
|
switch (os) {
|
2015-07-07 17:11:59 +08:00
|
|
|
case llvm::ELF::ELFOSABI_AIX:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::AIX);
|
|
|
|
break;
|
|
|
|
case llvm::ELF::ELFOSABI_FREEBSD:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::FreeBSD);
|
|
|
|
break;
|
|
|
|
case llvm::ELF::ELFOSABI_GNU:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::Linux);
|
|
|
|
break;
|
|
|
|
case llvm::ELF::ELFOSABI_NETBSD:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::NetBSD);
|
|
|
|
break;
|
|
|
|
case llvm::ELF::ELFOSABI_OPENBSD:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::OpenBSD);
|
|
|
|
break;
|
|
|
|
case llvm::ELF::ELFOSABI_SOLARIS:
|
|
|
|
m_triple.setOS(llvm::Triple::OSType::Solaris);
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
2015-06-05 21:03:08 +08:00
|
|
|
}
|
2016-09-17 03:09:19 +08:00
|
|
|
} else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
|
|
|
|
m_triple.setVendor(llvm::Triple::PC);
|
|
|
|
m_triple.setOS(llvm::Triple::Win32);
|
2015-11-06 09:43:36 +08:00
|
|
|
} else {
|
|
|
|
m_triple.setVendor(llvm::Triple::UnknownVendor);
|
|
|
|
m_triple.setOS(llvm::Triple::UnknownOS);
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2018-05-01 00:49:04 +08:00
|
|
|
// Fall back onto setting the machine type if the arch by name
|
|
|
|
// failed...
|
2011-09-21 11:57:31 +08:00
|
|
|
if (m_triple.getArch() == llvm::Triple::UnknownArch)
|
|
|
|
m_triple.setArch(core_def->machine);
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2018-05-01 08:05:54 +08:00
|
|
|
} else {
|
2018-05-01 08:42:17 +08:00
|
|
|
Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM));
|
2019-07-25 01:56:10 +08:00
|
|
|
LLDB_LOGF(log,
|
|
|
|
"Unable to find a core definition for cpu 0x%" PRIx32
|
|
|
|
" sub %" PRId32,
|
|
|
|
cpu, sub);
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
CoreUpdated(update_triple);
|
|
|
|
return IsValid();
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def)
|
|
|
|
return core_def->min_opcode_byte_size;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def)
|
|
|
|
return core_def->max_opcode_byte_size;
|
|
|
|
return 0;
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const {
|
2012-12-14 06:07:14 +08:00
|
|
|
return IsEqualTo(rhs, true);
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const {
|
2012-12-14 06:07:14 +08:00
|
|
|
return IsEqualTo(rhs, false);
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
|
|
|
|
2018-12-06 08:43:55 +08:00
|
|
|
static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
|
2016-04-25 23:51:45 +08:00
|
|
|
llvm::Triple::EnvironmentType rhs) {
|
|
|
|
if (lhs == rhs)
|
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2016-04-25 23:51:45 +08:00
|
|
|
// If any of the environment is unknown then they are compatible
|
|
|
|
if (lhs == llvm::Triple::UnknownEnvironment ||
|
|
|
|
rhs == llvm::Triple::UnknownEnvironment)
|
2012-11-04 11:20:05 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2016-04-25 23:51:45 +08:00
|
|
|
// If one of the environment is Android and the other one is EABI then they
|
2018-05-01 00:49:04 +08:00
|
|
|
// are considered to be compatible. This is required as a workaround for
|
|
|
|
// shared libraries compiled for Android without the NOTE section indicating
|
|
|
|
// that they are using the Android ABI.
|
2016-04-25 23:51:45 +08:00
|
|
|
if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
|
2016-04-26 09:08:59 +08:00
|
|
|
(rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
|
|
|
|
(lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
|
|
|
|
(rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
|
|
|
|
(lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
|
|
|
|
(rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
|
2016-04-25 23:51:45 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2016-04-25 23:51:45 +08:00
|
|
|
return false;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2016-04-25 23:51:45 +08:00
|
|
|
|
|
|
|
bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const {
|
|
|
|
// explicitly ignoring m_distribution_id in this method.
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
if (GetByteOrder() != rhs.GetByteOrder())
|
2016-04-25 23:51:45 +08:00
|
|
|
return false;
|
|
|
|
|
2012-12-14 06:07:14 +08:00
|
|
|
const ArchSpec::Core lhs_core = GetCore();
|
|
|
|
const ArchSpec::Core rhs_core = rhs.GetCore();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2012-12-14 06:07:14 +08:00
|
|
|
const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match);
|
2014-01-18 11:02:39 +08:00
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core_match) {
|
|
|
|
const llvm::Triple &lhs_triple = GetTriple();
|
|
|
|
const llvm::Triple &rhs_triple = rhs.GetTriple();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
|
|
|
|
const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
|
|
|
|
if (lhs_triple_vendor != rhs_triple_vendor) {
|
2015-11-06 09:43:36 +08:00
|
|
|
const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
|
|
|
|
const bool lhs_vendor_specified = TripleVendorWasSpecified();
|
2018-05-01 00:49:04 +08:00
|
|
|
// Both architectures had the vendor specified, so if they aren't equal
|
|
|
|
// then we return false
|
2015-11-06 09:43:36 +08:00
|
|
|
if (rhs_vendor_specified && lhs_vendor_specified)
|
2012-11-04 11:20:05 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Only fail if both vendor types are not unknown
|
|
|
|
if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
|
|
|
|
rhs_triple_vendor != llvm::Triple::UnknownVendor)
|
2016-04-25 23:51:45 +08:00
|
|
|
return false;
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
|
|
|
|
const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
|
|
|
|
if (lhs_triple_os != rhs_triple_os) {
|
2015-11-06 09:43:36 +08:00
|
|
|
const bool rhs_os_specified = rhs.TripleOSWasSpecified();
|
|
|
|
const bool lhs_os_specified = TripleOSWasSpecified();
|
2018-05-01 00:49:04 +08:00
|
|
|
// Both architectures had the OS specified, so if they aren't equal then
|
|
|
|
// we return false
|
2015-11-06 09:43:36 +08:00
|
|
|
if (rhs_os_specified && lhs_os_specified)
|
2012-11-04 11:20:05 +08:00
|
|
|
return false;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-07-11 07:33:37 +08:00
|
|
|
// Only fail if both os types are not unknown
|
|
|
|
if (lhs_triple_os != llvm::Triple::UnknownOS &&
|
|
|
|
rhs_triple_os != llvm::Triple::UnknownOS)
|
|
|
|
return false;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
const llvm::Triple::EnvironmentType lhs_triple_env =
|
|
|
|
lhs_triple.getEnvironment();
|
|
|
|
const llvm::Triple::EnvironmentType rhs_triple_env =
|
|
|
|
rhs_triple.getEnvironment();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2018-12-15 08:15:33 +08:00
|
|
|
return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
2014-07-11 07:33:37 +08:00
|
|
|
return false;
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
|
|
|
|
2017-04-20 20:30:18 +08:00
|
|
|
void ArchSpec::UpdateCore() {
|
|
|
|
llvm::StringRef arch_name(m_triple.getArchName());
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(arch_name);
|
|
|
|
if (core_def) {
|
|
|
|
m_core = core_def->core;
|
2018-05-01 00:49:04 +08:00
|
|
|
// Set the byte order to the default byte order for an architecture. This
|
|
|
|
// can be modified if needed for cases when cores handle both big and
|
|
|
|
// little endian
|
2017-04-20 20:30:18 +08:00
|
|
|
m_byte_order = core_def->default_byte_order;
|
|
|
|
} else {
|
|
|
|
Clear();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Helper methods.
|
|
|
|
|
|
|
|
void ArchSpec::CoreUpdated(bool update_triple) {
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition(m_core);
|
|
|
|
if (core_def) {
|
|
|
|
if (update_triple)
|
|
|
|
m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
|
|
|
|
m_byte_order = core_def->default_byte_order;
|
|
|
|
} else {
|
|
|
|
if (update_triple)
|
|
|
|
m_triple = llvm::Triple();
|
|
|
|
m_byte_order = eByteOrderInvalid;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Operators.
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
|
|
|
|
bool try_inverse, bool enforce_exact_match) {
|
|
|
|
if (core1 == core2)
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
switch (core1) {
|
2014-02-19 19:16:46 +08:00
|
|
|
case ArchSpec::kCore_any:
|
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2014-07-12 08:11:34 +08:00
|
|
|
case ArchSpec::eCore_arm_generic:
|
|
|
|
if (enforce_exact_match)
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
2016-02-16 12:14:33 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::kCore_arm_any:
|
|
|
|
if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2012-05-08 09:45:38 +08:00
|
|
|
if (core2 >= ArchSpec::kCore_thumb_first &&
|
|
|
|
core2 <= ArchSpec::kCore_thumb_last)
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2012-05-08 09:45:38 +08:00
|
|
|
if (core2 == ArchSpec::kCore_arm_any)
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::kCore_x86_32_any:
|
|
|
|
if ((core2 >= ArchSpec::kCore_x86_32_first &&
|
|
|
|
core2 <= ArchSpec::kCore_x86_32_last) ||
|
|
|
|
(core2 == ArchSpec::kCore_x86_32_any))
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2014-07-29 00:44:49 +08:00
|
|
|
case ArchSpec::kCore_x86_64_any:
|
|
|
|
if ((core2 >= ArchSpec::kCore_x86_64_first &&
|
|
|
|
core2 <= ArchSpec::kCore_x86_64_last) ||
|
|
|
|
(core2 == ArchSpec::kCore_x86_64_any))
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::kCore_ppc_any:
|
|
|
|
if ((core2 >= ArchSpec::kCore_ppc_first &&
|
|
|
|
core2 <= ArchSpec::kCore_ppc_last) ||
|
|
|
|
(core2 == ArchSpec::kCore_ppc_any))
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::kCore_ppc64_any:
|
|
|
|
if ((core2 >= ArchSpec::kCore_ppc64_first &&
|
|
|
|
core2 <= ArchSpec::kCore_ppc64_last) ||
|
|
|
|
(core2 == ArchSpec::kCore_ppc64_any))
|
2015-06-26 06:37:57 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2013-09-28 07:21:54 +08:00
|
|
|
case ArchSpec::eCore_arm_armv6m:
|
2012-11-04 11:20:05 +08:00
|
|
|
if (!enforce_exact_match) {
|
2014-07-12 08:11:34 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_generic)
|
2012-11-04 11:20:05 +08:00
|
|
|
return true;
|
2014-07-12 08:11:34 +08:00
|
|
|
try_inverse = false;
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv6m)
|
2012-11-04 11:20:05 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2014-02-19 19:16:46 +08:00
|
|
|
case ArchSpec::kCore_hexagon_any:
|
|
|
|
if ((core2 >= ArchSpec::kCore_hexagon_first &&
|
|
|
|
core2 <= ArchSpec::kCore_hexagon_last) ||
|
|
|
|
(core2 == ArchSpec::kCore_hexagon_any))
|
2014-07-15 06:53:02 +08:00
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2015-10-09 05:48:35 +08:00
|
|
|
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
|
2018-05-01 00:49:04 +08:00
|
|
|
// Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
|
|
|
|
// ARMv7E-M - armv7em
|
2013-03-08 09:20:17 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7em:
|
2014-08-28 22:32:43 +08:00
|
|
|
if (!enforce_exact_match) {
|
2014-07-12 08:11:34 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_generic)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7m)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv6m)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
try_inverse = true;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2015-10-09 05:48:35 +08:00
|
|
|
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
|
2018-05-01 00:49:04 +08:00
|
|
|
// Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 -
|
|
|
|
// ARMv7E-M - armv7em
|
2015-06-26 06:37:57 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7m:
|
2014-08-28 22:32:43 +08:00
|
|
|
if (!enforce_exact_match) {
|
2014-07-12 08:11:34 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_generic)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv6m)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7em)
|
2014-08-28 22:32:43 +08:00
|
|
|
return true;
|
2015-06-26 06:37:57 +08:00
|
|
|
try_inverse = true;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
2012-11-04 11:20:05 +08:00
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7f:
|
2012-08-29 06:53:40 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7k:
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7s:
|
2019-11-13 08:30:25 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7l:
|
|
|
|
case ArchSpec::eCore_arm_armv8l:
|
2015-07-13 17:52:06 +08:00
|
|
|
if (!enforce_exact_match) {
|
2014-07-12 08:11:34 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_generic)
|
2012-05-08 09:45:38 +08:00
|
|
|
return true;
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
2015-07-13 17:52:06 +08:00
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
2012-05-08 09:45:38 +08:00
|
|
|
|
2014-07-29 00:44:49 +08:00
|
|
|
case ArchSpec::eCore_x86_64_x86_64h:
|
2013-09-28 07:21:54 +08:00
|
|
|
if (!enforce_exact_match) {
|
2014-02-19 19:16:46 +08:00
|
|
|
try_inverse = false;
|
2015-06-26 06:37:57 +08:00
|
|
|
if (core2 == ArchSpec::eCore_x86_64_x86_64)
|
2014-07-12 08:11:34 +08:00
|
|
|
return true;
|
2014-07-15 06:53:02 +08:00
|
|
|
}
|
2014-08-28 22:32:43 +08:00
|
|
|
break;
|
|
|
|
|
2015-07-13 17:52:06 +08:00
|
|
|
case ArchSpec::eCore_arm_armv8:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 == ArchSpec::eCore_arm_arm64)
|
|
|
|
return true;
|
|
|
|
if (core2 == ArchSpec::eCore_arm_aarch64)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_arm_aarch64:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 == ArchSpec::eCore_arm_arm64)
|
|
|
|
return true;
|
|
|
|
if (core2 == ArchSpec::eCore_arm_armv8)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
2016-02-26 09:20:20 +08:00
|
|
|
break;
|
2015-07-13 17:52:06 +08:00
|
|
|
|
2015-06-03 18:14:24 +08:00
|
|
|
case ArchSpec::eCore_arm_arm64:
|
2015-07-13 17:52:06 +08:00
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 == ArchSpec::eCore_arm_aarch64)
|
2015-06-03 18:14:24 +08:00
|
|
|
return true;
|
2015-07-13 17:52:06 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv8)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
2016-02-26 09:20:20 +08:00
|
|
|
break;
|
2015-07-13 17:52:06 +08:00
|
|
|
|
2019-10-17 03:14:49 +08:00
|
|
|
case ArchSpec::eCore_arm_arm64_32:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 == ArchSpec::eCore_arm_generic)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2015-07-13 17:52:06 +08:00
|
|
|
case ArchSpec::eCore_mips32:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips32_last)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
2016-02-26 09:20:20 +08:00
|
|
|
break;
|
2015-07-13 17:52:06 +08:00
|
|
|
|
2015-06-03 18:14:24 +08:00
|
|
|
case ArchSpec::eCore_mips32el:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32el_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips32el_last)
|
|
|
|
return true;
|
2017-03-31 19:14:02 +08:00
|
|
|
try_inverse = true;
|
2015-06-03 18:14:24 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips64:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips32_last)
|
|
|
|
return true;
|
|
|
|
if (core2 >= ArchSpec::kCore_mips64_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips64_last)
|
|
|
|
return true;
|
|
|
|
try_inverse = false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2015-07-13 17:52:06 +08:00
|
|
|
case ArchSpec::eCore_mips64el:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32el_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips32el_last)
|
|
|
|
return true;
|
|
|
|
if (core2 >= ArchSpec::kCore_mips64el_first &&
|
|
|
|
core2 <= ArchSpec::kCore_mips64el_last)
|
|
|
|
return true;
|
2014-08-28 22:32:43 +08:00
|
|
|
try_inverse = false;
|
2015-07-13 17:52:06 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips64r2:
|
|
|
|
case ArchSpec::eCore_mips64r3:
|
|
|
|
case ArchSpec::eCore_mips64r5:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
|
|
|
|
return true;
|
|
|
|
if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
|
|
|
|
return true;
|
2014-08-28 22:32:43 +08:00
|
|
|
try_inverse = false;
|
2015-07-13 17:52:06 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips64r2el:
|
2015-06-03 18:14:24 +08:00
|
|
|
case ArchSpec::eCore_mips64r3el:
|
|
|
|
case ArchSpec::eCore_mips64r5el:
|
2015-07-13 17:52:06 +08:00
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
|
|
|
|
return true;
|
|
|
|
if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
|
|
|
|
return true;
|
2014-08-28 22:32:43 +08:00
|
|
|
try_inverse = false;
|
2015-07-13 17:52:06 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips32r2:
|
|
|
|
case ArchSpec::eCore_mips32r3:
|
|
|
|
case ArchSpec::eCore_mips32r5:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips32r2el:
|
|
|
|
case ArchSpec::eCore_mips32r3el:
|
|
|
|
case ArchSpec::eCore_mips32r5el:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ArchSpec::eCore_mips32r6:
|
|
|
|
if (!enforce_exact_match) {
|
|
|
|
if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::eCore_mips32r6el:
|
2014-08-28 22:32:43 +08:00
|
|
|
if (!enforce_exact_match) {
|
2015-07-13 17:52:06 +08:00
|
|
|
if (core2 == ArchSpec::eCore_mips32el ||
|
|
|
|
core2 == ArchSpec::eCore_mips32r6el)
|
2012-05-08 09:45:38 +08:00
|
|
|
return true;
|
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
break;
|
|
|
|
|
2015-06-03 18:14:24 +08:00
|
|
|
case ArchSpec::eCore_mips64r6:
|
2014-08-28 22:32:43 +08:00
|
|
|
if (!enforce_exact_match) {
|
2015-07-13 17:52:06 +08:00
|
|
|
if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
|
|
|
|
return true;
|
|
|
|
if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
|
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2015-06-03 18:14:24 +08:00
|
|
|
case ArchSpec::eCore_mips64r6el:
|
2014-08-28 22:32:43 +08:00
|
|
|
if (!enforce_exact_match) {
|
2015-07-13 17:52:06 +08:00
|
|
|
if (core2 == ArchSpec::eCore_mips32el ||
|
|
|
|
core2 == ArchSpec::eCore_mips32r6el)
|
|
|
|
return true;
|
|
|
|
if (core2 == ArchSpec::eCore_mips64el ||
|
|
|
|
core2 == ArchSpec::eCore_mips64r6el)
|
|
|
|
return true;
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2012-05-08 09:45:38 +08:00
|
|
|
if (try_inverse)
|
2012-11-04 11:20:05 +08:00
|
|
|
return cores_match(core2, core1, false, enforce_exact_match);
|
2012-05-08 09:45:38 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-06-09 00:52:24 +08:00
|
|
|
bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchSpec::Core lhs_core = lhs.GetCore();
|
|
|
|
const ArchSpec::Core rhs_core = rhs.GetCore();
|
|
|
|
return lhs_core < rhs_core;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2014-12-10 07:31:02 +08:00
|
|
|
|
2018-01-29 18:46:00 +08:00
|
|
|
|
|
|
|
bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
|
|
|
|
return lhs.GetCore() == rhs.GetCore();
|
|
|
|
}
|
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
bool ArchSpec::IsFullySpecifiedTriple() const {
|
|
|
|
const auto &user_specified_triple = GetTriple();
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
bool user_triple_fully_specified = false;
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) ||
|
|
|
|
TripleOSWasSpecified()) {
|
|
|
|
if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) ||
|
|
|
|
TripleVendorWasSpecified()) {
|
|
|
|
const unsigned unspecified = 0;
|
|
|
|
if (user_specified_triple.getOSMajorVersion() != unspecified) {
|
|
|
|
user_triple_fully_specified = true;
|
|
|
|
}
|
|
|
|
}
|
2016-09-07 04:57:50 +08:00
|
|
|
}
|
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
return user_triple_fully_specified;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ArchSpec::PiecewiseTripleCompare(
|
|
|
|
const ArchSpec &other, bool &arch_different, bool &vendor_different,
|
2017-10-26 05:05:31 +08:00
|
|
|
bool &os_different, bool &os_version_different, bool &env_different) const {
|
2015-11-06 09:43:36 +08:00
|
|
|
const llvm::Triple &me(GetTriple());
|
|
|
|
const llvm::Triple &them(other.GetTriple());
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
arch_different = (me.getArch() != them.getArch());
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
vendor_different = (me.getVendor() != them.getVendor());
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
os_different = (me.getOS() != them.getOS());
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
|
2016-09-07 04:57:50 +08:00
|
|
|
|
2015-11-06 09:43:36 +08:00
|
|
|
env_different = (me.getEnvironment() != them.getEnvironment());
|
|
|
|
}
|
|
|
|
|
2016-04-05 13:01:30 +08:00
|
|
|
bool ArchSpec::IsAlwaysThumbInstructions() const {
|
2017-05-12 12:51:55 +08:00
|
|
|
std::string Status;
|
2016-04-05 13:01:30 +08:00
|
|
|
if (GetTriple().getArch() == llvm::Triple::arm ||
|
|
|
|
GetTriple().getArch() == llvm::Triple::thumb) {
|
|
|
|
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M
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//
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// Cortex-M0 through Cortex-M7 are ARM processor cores which can only
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// execute thumb instructions. We map the cores to arch names like this:
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//
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2018-05-01 00:49:04 +08:00
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// Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
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// Cortex-M7: armv7em
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2016-09-07 04:57:50 +08:00
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2016-04-05 13:01:30 +08:00
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if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
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GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
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2018-09-07 09:28:48 +08:00
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GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
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GetCore() == ArchSpec::Core::eCore_thumbv7m ||
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GetCore() == ArchSpec::Core::eCore_thumbv7em ||
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GetCore() == ArchSpec::Core::eCore_thumbv6m) {
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2016-04-05 13:01:30 +08:00
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return true;
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}
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2019-10-16 05:05:06 +08:00
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// Windows on ARM is always thumb.
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if (GetTriple().isOSWindows())
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return true;
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2016-09-07 04:57:50 +08:00
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}
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2016-04-05 13:01:30 +08:00
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return false;
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}
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2019-12-04 15:27:43 +08:00
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void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
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2015-10-14 07:41:19 +08:00
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const llvm::Triple &triple = GetTriple();
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llvm::StringRef arch_str = triple.getArchName();
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llvm::StringRef vendor_str = triple.getVendorName();
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llvm::StringRef os_str = triple.getOSName();
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2016-04-06 01:29:19 +08:00
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llvm::StringRef environ_str = triple.getEnvironmentName();
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2016-09-07 04:57:50 +08:00
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2019-12-04 15:27:43 +08:00
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s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
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vendor_str.empty() ? "*" : vendor_str,
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os_str.empty() ? "*" : os_str);
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2016-09-07 04:57:50 +08:00
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2016-04-06 01:29:19 +08:00
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if (!environ_str.empty())
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2019-12-04 15:27:43 +08:00
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s << "-" << environ_str;
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2015-10-14 07:41:19 +08:00
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}
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