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llvm-project/llvm/test/CodeGen/X86/mmx-fold-load.ll

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Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
define i64 @t0(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t0:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1:[a-z]+]]), %mm0
; CHECK-NEXT: psllq (%[[REG2:[a-z]+]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
define i64 @t1(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t1:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psrlq (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32)
define i64 @t2(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t2:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psllw (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32)
define i64 @t3(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t3:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psrlw (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32)
define i64 @t4(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t4:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: pslld (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32)
define i64 @t5(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t5:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psrld (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32)
define i64 @t6(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t6:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psraw (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32)
define i64 @t7(<1 x i64>* %a, i32* %b) {
; CHECK-LABEL: t7:
Make this test not dependent upon the triple. All that was needed was some flexibility in the check line for the comment basic block. llvm-svn: 230400
2015-02-25 07:43:26 +08:00
; CHECK: # BB#0:{{.*}} %entry
Make this test even more OS and register allocation neutral. llvm-svn: 230404
2015-02-25 08:12:11 +08:00
; CHECK: movq (%[[REG1]]), %mm0
; CHECK-NEXT: psrad (%[[REG2]]), %mm0
[X86][MMX] Add tests for pslli, psrli and psrai intrinsics Add tests to cover the RR form of the pslli, psrli and psrai intrinsics. In the next commit, the loads are going to be folded and the instructions use the RM form. llvm-svn: 230224
2015-02-23 23:23:06 +08:00
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
%1 = load x86_mmx* %0, align 8
%2 = load i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
}
declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32)
[X86][MMX] Reapply: Add MMX instructions to foldable tables Reapply r230248. Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230499
2015-02-25 23:14:02 +08:00
define i64 @tt0(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt0:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddb (%[[REG3:[a-z]+]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
declare void @llvm.x86.mmx.emms()
define i64 @tt1(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt1:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddw (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
define i64 @tt2(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt2:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddd (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
define i64 @tt3(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt3:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddq (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
define i64 @tt4(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt4:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddusb (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
define i64 @tt5(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt5:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: paddusw (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
define i64 @tt6(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt6:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: psrlw (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx)
define i64 @tt7(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt7:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: psrld (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx)
define i64 @tt8(x86_mmx %t, x86_mmx* %q) {
; CHECK-LABEL: tt8:
; CHECK: # BB#0:{{.*}} %entry
; CHECK: psrlq (%[[REG3]]), %mm0
; CHECK-NEXT: movd %mm0, %rax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
%v = load x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
ret i64 %s
}
declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx)