maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Mips/macro-ddiv-bad.s

19 lines
713 B
ArmAsm
Raw Normal View History

[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
# RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
.text
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
ddivu $25, $11
# MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
ddivu $25, $0
# MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
2015-09-03 20:31:22 +08:00
[mips] Addition of a third operand to the instructions [d]div, [d]divu Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
2016-05-16 16:57:59 +08:00
ddivu $0,$0
# MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero