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llvm-project/llvm/test/CodeGen/AArch64/branch-relax-bcc.ll

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AArch64: Add missing branch relaxation tests The branch relaxation pass has the worst test coverage of any pass in AArch64. Add a few tests that hit some large pieces of code in the pass. llvm-svn: 277428
2016-08-02 15:41:05 +08:00
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
; CHECK-LABEL: invert_bcc:
BranchRelaxation: Fix handling of blocks with multiple conditional branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
2016-08-23 09:30:30 +08:00
; CHECK: fcmp s0, s1
[BranchRelaxation] Simplify offset computation and fix a bug in adjustBlockOffsets() If Start!=0, adjustBlockOffsets() may unnecessarily adjust the offset of Start. There is no correctness issue, but it can create more block splits.
2020-01-20 06:53:45 +08:00
; CHECK-NEXT: b.ne [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
BranchRelaxation: Fix handling of blocks with multiple conditional branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
2016-08-23 09:30:30 +08:00
; CHECK-NEXT: b [[BB1:LBB[0-9]+_[0-9]+]]
[BranchRelaxation] Simplify offset computation and fix a bug in adjustBlockOffsets() If Start!=0, adjustBlockOffsets() may unnecessarily adjust the offset of Start. There is no correctness issue, but it can create more block splits.
2020-01-20 06:53:45 +08:00
; CHECK-NEXT: [[JUMP_BB1]]:
BranchRelaxation: Fix handling of blocks with multiple conditional branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
2016-08-23 09:30:30 +08:00
; CHECK-NEXT: b.vc [[BB2:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[BB1]]
; CHECK: [[BB2]]: ; %bb2
AArch64: Add missing branch relaxation tests The branch relaxation pass has the worst test coverage of any pass in AArch64. Add a few tests that hit some large pieces of code in the pass. llvm-svn: 277428
2016-08-02 15:41:05 +08:00
; CHECK: mov w{{[0-9]+}}, #9
; CHECK: ret
BranchRelaxation: Fix handling of blocks with multiple conditional branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
2016-08-23 09:30:30 +08:00
; CHECK: [[BB1]]: ; %bb1
AArch64: Add missing branch relaxation tests The branch relaxation pass has the worst test coverage of any pass in AArch64. Add a few tests that hit some large pieces of code in the pass. llvm-svn: 277428
2016-08-02 15:41:05 +08:00
; CHECK: mov w{{[0-9]+}}, #42
; CHECK: ret
define i32 @invert_bcc(float %x, float %y) #0 {
%1 = fcmp ueq float %x, %y
br i1 %1, label %bb1, label %bb2
bb2:
call void asm sideeffect
"nop
nop",
""() #0
store volatile i32 9, i32* undef
ret i32 1
bb1:
store volatile i32 42, i32* undef
ret i32 0
}
declare i32 @foo() #0
; CHECK-LABEL: _block_split:
; CHECK: cmp w0, #5
[BranchRelaxation] Simplify offset computation and fix a bug in adjustBlockOffsets() If Start!=0, adjustBlockOffsets() may unnecessarily adjust the offset of Start. There is no correctness issue, but it can create more block splits.
2020-01-20 06:53:45 +08:00
; CHECK-NEXT: b.ne [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
AArch64: Add missing branch relaxation tests The branch relaxation pass has the worst test coverage of any pass in AArch64. Add a few tests that hit some large pieces of code in the pass. llvm-svn: 277428
2016-08-02 15:41:05 +08:00
; CHECK-NEXT: b [[IF_THEN_BB:LBB[0-9]+_[0-9]+]]
; CHECK: [[LOR_LHS_FALSE_BB]]:
; CHECK: cmp w{{[0-9]+}}, #16
; CHECK-NEXT: b.le [[IF_THEN_BB]]
; CHECK-NEXT: b [[IF_END_BB:LBB[0-9]+_[0-9]+]]
; CHECK: [[IF_THEN_BB]]:
; CHECK: bl _foo
; CHECK-NOT: b L
; CHECK: [[IF_END_BB]]:
[AArch64] Prefer "mov" over "orr" to materialize constants. This is generally more readable due to the way the assembler aliases work. (This causes a lot of test changes, but it's not really as scary as it looks at first glance; it's just mechanically changing a bunch of checks for orr to check for mov instead.) Differential Revision: https://reviews.llvm.org/D59720 llvm-svn: 356954
2019-03-26 05:25:28 +08:00
; CHECK: mov{{.*}}, #7
AArch64: Add missing branch relaxation tests The branch relaxation pass has the worst test coverage of any pass in AArch64. Add a few tests that hit some large pieces of code in the pass. llvm-svn: 277428
2016-08-02 15:41:05 +08:00
; CHECK: ret
define i32 @block_split(i32 %a, i32 %b) #0 {
entry:
%cmp = icmp eq i32 %a, 5
br i1 %cmp, label %if.then, label %lor.lhs.false
lor.lhs.false: ; preds = %entry
%cmp1 = icmp slt i32 %b, 7
%mul = shl nsw i32 %b, 1
%add = add nsw i32 %b, 1
%cond = select i1 %cmp1, i32 %mul, i32 %add
%cmp2 = icmp slt i32 %cond, 17
br i1 %cmp2, label %if.then, label %if.end
if.then: ; preds = %lor.lhs.false, %entry
%call = tail call i32 @foo()
br label %if.end
if.end: ; preds = %if.then, %lor.lhs.false
ret i32 7
}
attributes #0 = { nounwind }