2011-09-24 09:40:18 +08:00
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//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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2011-09-29 01:50:27 +08:00
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2011-09-30 10:08:54 +08:00
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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2011-12-20 03:44:09 +08:00
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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2011-09-30 11:18:46 +08:00
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2014-04-05 00:21:59 +08:00
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// Node immediate fits as 10-bit sign extended on target immediate.
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// e.g. seqi, snei
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def immSExt10_64 : PatLeaf<(i64 imm),
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[{ return isInt<10>(N->getSExtValue()); }]>;
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2014-06-12 21:39:06 +08:00
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def immZExt16_64 : PatLeaf<(i64 imm),
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2016-04-22 21:19:22 +08:00
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[{ return isUInt<16>(N->getZExtValue()); }]>;
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2014-06-12 21:39:06 +08:00
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2015-01-21 00:10:51 +08:00
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def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
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// Transformation function: get log2 of low 32 bits of immediate
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def Log2LO : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) N->getZExtValue()));
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}]>;
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// Transformation function: get log2 of high 32 bits of immediate
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def Log2HI : SDNodeXForm<imm, [{
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return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
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}]>;
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// Predicate: True if immediate is a power of 2 and fits 32 bits
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def PowerOf2LO : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
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}
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else
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return false;
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}]>;
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// Predicate: True if immediate is a power of 2 and exceeds 32 bits
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def PowerOf2HI : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i64) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
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}
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else
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return false;
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}]>;
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2017-08-30 19:25:38 +08:00
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def PowerOf2LO_i32 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32) {
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uint64_t Imm = N->getZExtValue();
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return isPowerOf2_32(Imm) && isUInt<32>(Imm);
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}
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else
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return false;
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}]>;
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2016-04-13 23:07:45 +08:00
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def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
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return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
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}]>;
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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2013-08-21 05:08:22 +08:00
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let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
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def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
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def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
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def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
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def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
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def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
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def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
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def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
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2011-11-11 12:14:30 +08:00
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}
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2013-05-01 07:22:09 +08:00
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/// Pseudo instructions for loading and storing accumulator registers.
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2016-06-14 17:35:29 +08:00
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let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
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2013-08-21 05:08:22 +08:00
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def LOAD_ACC128 : Load<"", ACC128>;
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def STORE_ACC128 : Store<"", ACC128>;
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2013-03-30 08:54:52 +08:00
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}
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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2012-04-18 02:03:21 +08:00
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let DecoderNamespace = "Mips64" in {
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2011-09-30 10:08:54 +08:00
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/// Arithmetic Instructions (ALU Immediate)
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2016-06-14 17:35:29 +08:00
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>,
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ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6;
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2016-04-08 15:27:26 +08:00
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let AdditionalPredicates = [NotInMicroMips] in {
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def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
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II_DADDIU, immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
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}
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2016-03-02 04:25:43 +08:00
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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SLTI_FM<0xa>;
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
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SLTI_FM<0xb>;
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2014-01-16 23:57:05 +08:00
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def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
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2013-07-31 08:57:41 +08:00
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ADDI_FM<0xc>;
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2014-01-16 23:57:05 +08:00
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def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xd>;
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2014-01-16 23:57:05 +08:00
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def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xe>;
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2016-02-01 23:13:31 +08:00
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM;
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2013-08-07 07:01:10 +08:00
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}
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2011-09-30 10:08:54 +08:00
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2011-09-30 04:37:56 +08:00
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/// Arithmetic Instructions (3-Operand, R-Type)
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2016-04-08 15:27:26 +08:00
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let AdditionalPredicates = [NotInMicroMips] in {
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def DADD : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>,
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ADD_FM<0, 0x2c>, ISA_MIPS3;
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def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
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ADD_FM<0, 0x2d>, ISA_MIPS3;
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2016-04-27 19:31:44 +08:00
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def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
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ISA_MIPS3;
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def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
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ISA_MIPS3;
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2016-04-08 15:27:26 +08:00
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}
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2013-08-07 06:35:29 +08:00
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let isCodeGenOnly = 1 in {
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2016-03-02 04:25:43 +08:00
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
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2013-08-07 07:08:38 +08:00
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def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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2013-08-07 06:35:29 +08:00
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}
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2011-09-30 11:18:46 +08:00
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/// Shift Instructions
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2016-05-11 19:17:04 +08:00
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let AdditionalPredicates = [NotInMicroMips] in {
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2016-06-16 15:06:25 +08:00
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def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
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shl, immZExt6>,
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SRA_FM<0x38, 0>, ISA_MIPS3;
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2016-06-27 16:23:28 +08:00
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def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
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srl, immZExt6>,
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2014-05-09 21:02:27 +08:00
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SRA_FM<0x3a, 0>, ISA_MIPS3;
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2016-06-16 15:06:25 +08:00
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def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
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sra, immZExt6>,
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2014-05-09 21:02:27 +08:00
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SRA_FM<0x3b, 0>, ISA_MIPS3;
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2016-06-16 15:06:25 +08:00
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def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
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SRLV_FM<0x14, 0>, ISA_MIPS3;
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def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
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2016-05-11 19:17:04 +08:00
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SRLV_FM<0x17, 0>, ISA_MIPS3;
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2016-06-27 16:23:28 +08:00
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def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
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SRLV_FM<0x16, 0>, ISA_MIPS3;
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2016-06-16 15:06:25 +08:00
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def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
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II_DSLL32>,
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2016-05-11 19:17:04 +08:00
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SRA_FM<0x3c, 0>, ISA_MIPS3;
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2016-06-27 16:23:28 +08:00
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def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
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II_DSRL32>,
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SRA_FM<0x3e, 0>, ISA_MIPS3;
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2016-06-16 15:06:25 +08:00
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def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
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II_DSRA32>,
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2016-05-11 19:17:04 +08:00
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SRA_FM<0x3f, 0>, ISA_MIPS3;
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2013-08-07 07:01:10 +08:00
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2011-10-01 02:51:46 +08:00
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// Rotate Instructions
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2016-06-16 15:06:25 +08:00
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def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR,
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rotr, immZExt6>,
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SRA_FM<0x3a, 1>, ISA_MIPS64R2;
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def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV,
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rotr>,
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SRLV_FM<0x16, 1>, ISA_MIPS64R2;
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def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd,
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II_DROTR32>,
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SRA_FM<0x3e, 1>, ISA_MIPS64R2;
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}
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2011-10-01 02:51:46 +08:00
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2011-10-11 08:27:28 +08:00
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/// Load and Store Instructions
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2012-02-28 15:46:26 +08:00
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/// aligned
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2014-01-21 23:21:14 +08:00
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def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
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def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
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def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
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def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
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def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
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2014-01-23 18:31:31 +08:00
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def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
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def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
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def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
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2013-08-07 07:01:10 +08:00
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}
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2016-06-27 16:23:28 +08:00
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let AdditionalPredicates = [NotInMicroMips] in {
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def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
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LW_FM<0x27>, ISA_MIPS3;
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def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
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LW_FM<0x37>, ISA_MIPS3;
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def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
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LW_FM<0x3f>, ISA_MIPS3;
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}
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2011-10-11 08:27:28 +08:00
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2012-06-02 08:04:19 +08:00
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/// load/store left/right
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2014-01-21 23:21:14 +08:00
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def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
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def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
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2014-01-23 18:31:31 +08:00
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def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
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2013-08-07 07:01:10 +08:00
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}
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2013-01-12 09:03:14 +08:00
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2014-05-09 21:02:27 +08:00
|
|
|
def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
|
2014-05-23 21:18:02 +08:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 21:02:27 +08:00
|
|
|
def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
|
2014-05-23 21:18:02 +08:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 21:02:27 +08:00
|
|
|
def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
|
2014-05-23 21:18:02 +08:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 21:02:27 +08:00
|
|
|
def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
|
2014-05-23 21:18:02 +08:00
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
2012-06-02 08:04:19 +08:00
|
|
|
|
2011-11-11 12:14:30 +08:00
|
|
|
/// Load-linked, Store-conditional
|
2016-06-27 16:23:28 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
}
|
2014-06-16 21:13:03 +08:00
|
|
|
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-11-11 12:14:30 +08:00
|
|
|
|
2016-06-14 19:29:28 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips],
|
|
|
|
|
DecoderNamespace = "Mips32_64_PTR64" in {
|
|
|
|
|
def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64,
|
|
|
|
|
ISA_MIPS2_NOT_32R6_64R6;
|
|
|
|
|
def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64,
|
|
|
|
|
ISA_MIPS2_NOT_32R6_64R6;
|
2016-08-04 17:17:07 +08:00
|
|
|
def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64;
|
2016-06-14 19:29:28 +08:00
|
|
|
}
|
|
|
|
|
|
2016-08-04 17:17:07 +08:00
|
|
|
def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
|
|
|
|
|
|
2011-10-12 02:49:17 +08:00
|
|
|
/// Jump and Branch Instructions
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in {
|
2014-07-09 18:21:59 +08:00
|
|
|
def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
|
|
|
|
|
def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
|
|
|
|
|
def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
|
|
|
|
|
def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
|
|
|
|
|
def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
|
|
|
|
|
def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
|
|
|
|
|
def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
|
2013-08-07 07:01:10 +08:00
|
|
|
}
|
2012-01-04 11:02:47 +08:00
|
|
|
|
2016-08-18 21:22:43 +08:00
|
|
|
def TAILCALLREG64 : TailCallReg<GPR64Opnd>;
|
2016-08-04 17:17:07 +08:00
|
|
|
|
[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
llvm-svn: 212604
2014-07-09 18:16:07 +08:00
|
|
|
def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
|
2014-07-09 18:21:59 +08:00
|
|
|
def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
|
[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
llvm-svn: 212604
2014-07-09 18:16:07 +08:00
|
|
|
|
2011-10-04 04:01:11 +08:00
|
|
|
/// Multiply and Divide Instructions.
|
2016-05-06 16:24:14 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
|
|
MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
|
|
MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
}
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
2014-06-12 18:44:10 +08:00
|
|
|
II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
2014-06-12 18:44:10 +08:00
|
|
|
II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
|
2016-04-13 16:02:26 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
|
|
MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
|
|
MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
}
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
2014-06-12 18:44:10 +08:00
|
|
|
II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
2014-06-12 18:44:10 +08:00
|
|
|
II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-10-04 04:01:11 +08:00
|
|
|
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in {
|
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
div $1, $2
mflo $3
is now:
div $3, $1, $2
This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.
Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.
MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.
Reviewers: vmedic, zoran.jovanovic, jkolek
Reviewed By: jkolek
Differential Revision: http://reviews.llvm.org/D3896
llvm-svn: 210760
2014-06-12 18:44:10 +08:00
|
|
|
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
|
|
|
|
|
ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
|
2011-10-04 03:28:44 +08:00
|
|
|
|
2012-01-25 05:41:09 +08:00
|
|
|
/// Sign Ext In Register Instructions.
|
2014-05-12 20:28:15 +08:00
|
|
|
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
|
|
|
|
|
ISA_MIPS32R2;
|
|
|
|
|
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
|
|
|
|
|
ISA_MIPS32R2;
|
2013-08-07 07:01:10 +08:00
|
|
|
}
|
2012-01-25 05:41:09 +08:00
|
|
|
|
2011-10-04 05:16:50 +08:00
|
|
|
/// Count Leading
|
2016-06-16 15:06:25 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
2016-08-24 21:00:47 +08:00
|
|
|
def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>,
|
|
|
|
|
CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
|
|
|
|
|
def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>,
|
|
|
|
|
CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
|
2011-10-04 05:16:50 +08:00
|
|
|
|
2011-12-21 07:56:43 +08:00
|
|
|
/// Double Word Swap Bytes/HalfWords
|
2016-08-24 21:00:47 +08:00
|
|
|
def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>,
|
|
|
|
|
ISA_MIPS64R2;
|
|
|
|
|
def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>,
|
|
|
|
|
ISA_MIPS64R2;
|
2016-05-11 19:17:04 +08:00
|
|
|
}
|
2012-12-22 07:21:32 +08:00
|
|
|
|
2013-08-21 05:08:22 +08:00
|
|
|
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
|
2011-12-21 07:56:43 +08:00
|
|
|
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in
|
2013-08-09 05:37:32 +08:00
|
|
|
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
|
2011-12-08 07:31:26 +08:00
|
|
|
|
2015-08-12 20:45:16 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
2016-02-29 23:26:54 +08:00
|
|
|
// The 'pos + size' constraints are enforced by the code that lowers into
|
|
|
|
|
// MipsISD::Ext.
|
|
|
|
|
def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
|
2016-06-23 17:06:20 +08:00
|
|
|
immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>,
|
|
|
|
|
ISA_MIPS64R2;
|
2016-02-29 23:26:54 +08:00
|
|
|
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
|
2016-06-23 17:06:20 +08:00
|
|
|
immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2;
|
2015-12-21 21:08:58 +08:00
|
|
|
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
|
2016-06-23 17:06:20 +08:00
|
|
|
immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
|
|
|
|
|
ISA_MIPS64R2;
|
2017-09-14 23:17:50 +08:00
|
|
|
// The 'pos + size' constraints for code generation are enforced by the
|
|
|
|
|
// code that lowers into MipsISD::Ins.
|
|
|
|
|
// For assembly parsing, we alias dinsu and dinsm to dins, and match by
|
|
|
|
|
// operand were possible then check the 'pos + size' in MipsAsmParser.
|
|
|
|
|
// We override the generated decoder to enforce that dins always comes out
|
|
|
|
|
// for dinsm and dinsu like binutils.
|
|
|
|
|
let DecoderMethod = "DecodeDINS" in {
|
|
|
|
|
def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1,
|
|
|
|
|
immZExt5, immZExt5Plus1, MipsIns>, EXT_FM<7>,
|
|
|
|
|
ISA_MIPS64R2;
|
|
|
|
|
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1,
|
|
|
|
|
immZExt5Plus32, immZExt5Plus1, MipsIns>,
|
|
|
|
|
EXT_FM<6>, ISA_MIPS64R2;
|
|
|
|
|
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
|
|
|
|
|
immZExt5, immZExtRange2To64, MipsIns>,
|
|
|
|
|
EXT_FM<5>, ISA_MIPS64R2;
|
|
|
|
|
}
|
2015-08-12 20:45:16 +08:00
|
|
|
}
|
2013-09-07 08:02:02 +08:00
|
|
|
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt),
|
|
|
|
|
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos,
|
|
|
|
|
uimm5_plus1:$size),
|
|
|
|
|
"dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
|
|
|
|
|
EXT_FM<3>, ISA_MIPS64R2;
|
|
|
|
|
}
|
|
|
|
|
|
2012-08-07 08:35:22 +08:00
|
|
|
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
2013-08-07 07:08:38 +08:00
|
|
|
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"dsll\t$rd, $rt, 32", [], II_DSLL>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2012-08-07 08:35:22 +08:00
|
|
|
}
|
2014-03-20 19:51:58 +08:00
|
|
|
|
2014-05-28 02:53:06 +08:00
|
|
|
// We need the following pseudo instruction to avoid offset calculation for
|
2014-04-30 23:06:25 +08:00
|
|
|
// long branches. See the comment in file MipsLongBranch.cpp for detailed
|
|
|
|
|
// explanation.
|
|
|
|
|
|
|
|
|
|
// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
|
2014-05-28 02:53:06 +08:00
|
|
|
// where %PART may be %hi or %lo, depending on the relocation kind
|
2014-04-30 23:06:25 +08:00
|
|
|
// that $tgt is annotated with.
|
|
|
|
|
def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
|
|
|
|
|
(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
|
|
|
|
|
|
2015-05-29 00:23:16 +08:00
|
|
|
// Cavium Octeon cnMIPS instructions
|
|
|
|
|
let DecoderNamespace = "CnMips",
|
2016-03-24 19:40:48 +08:00
|
|
|
// FIXME: The lack of HasStdEnc is probably a bug
|
|
|
|
|
EncodingPredicates = []<Predicate> in {
|
2014-03-20 19:51:58 +08:00
|
|
|
|
|
|
|
|
class Count1s<string opstr, RegisterOperand RO>:
|
|
|
|
|
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
2014-04-03 02:40:43 +08:00
|
|
|
[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
|
|
}
|
|
|
|
|
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO,
|
|
|
|
|
PatFrag PosImm, SDPatternOperator Op = null_frag>:
|
|
|
|
|
InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
|
|
|
|
|
!strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"),
|
|
|
|
|
[(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))],
|
2016-08-24 21:00:47 +08:00
|
|
|
itin, FrmR, opstr> {
|
2014-04-03 02:40:43 +08:00
|
|
|
let TwoOperandAliasConstraint = "$rt = $rs";
|
|
|
|
|
}
|
2014-03-20 19:51:58 +08:00
|
|
|
|
|
|
|
|
class SetCC64_R<string opstr, PatFrag cond_op> :
|
|
|
|
|
InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
|
|
|
|
|
!strconcat(opstr, "\t$rd, $rs, $rt"),
|
2016-03-02 04:25:43 +08:00
|
|
|
[(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
|
|
|
|
|
GPR64Opnd:$rt)))],
|
2014-04-03 02:40:43 +08:00
|
|
|
II_SEQ_SNE, FrmR, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rd = $rs";
|
|
|
|
|
}
|
2014-03-20 19:51:58 +08:00
|
|
|
|
2014-04-05 00:21:59 +08:00
|
|
|
class SetCC64_I<string opstr, PatFrag cond_op>:
|
|
|
|
|
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
|
|
|
|
|
!strconcat(opstr, "\t$rt, $rs, $imm10"),
|
2016-03-02 04:25:43 +08:00
|
|
|
[(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
|
|
|
|
|
immSExt10_64:$imm10)))],
|
2014-04-05 00:21:59 +08:00
|
|
|
II_SEQI_SNEI, FrmI, opstr> {
|
|
|
|
|
let TwoOperandAliasConstraint = "$rt = $rs";
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-21 00:10:51 +08:00
|
|
|
class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
|
2015-11-27 00:35:41 +08:00
|
|
|
RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
|
|
|
|
|
InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
|
2015-01-21 00:10:51 +08:00
|
|
|
!strconcat(opstr, "\t$rs, $p, $offset"),
|
2016-03-02 04:25:43 +08:00
|
|
|
[(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
|
2015-09-22 21:36:28 +08:00
|
|
|
bb:$offset)], II_BBIT, FrmI, opstr> {
|
2015-01-21 00:10:51 +08:00
|
|
|
let isBranch = 1;
|
|
|
|
|
let isTerminator = 1;
|
|
|
|
|
let hasDelaySlot = 1;
|
|
|
|
|
let Defs = [AT];
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-24 21:00:47 +08:00
|
|
|
class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
|
2015-05-29 00:23:16 +08:00
|
|
|
InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
|
2016-08-24 21:00:47 +08:00
|
|
|
!strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>;
|
2015-05-29 00:23:16 +08:00
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
// Unsigned Byte Add
|
2014-04-03 02:40:43 +08:00
|
|
|
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
|
2016-03-24 19:40:48 +08:00
|
|
|
ADD_FM<0x1c, 0x28>, ASE_CNMIPS {
|
|
|
|
|
let Pattern = [(set GPR64Opnd:$rd,
|
|
|
|
|
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))];
|
|
|
|
|
}
|
2014-03-20 19:51:58 +08:00
|
|
|
|
2015-01-21 00:10:51 +08:00
|
|
|
// Branch on Bit Clear /+32
|
2015-11-27 00:35:41 +08:00
|
|
|
def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
|
2016-03-24 19:40:48 +08:00
|
|
|
uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS;
|
2015-11-27 00:35:41 +08:00
|
|
|
def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
|
2016-03-24 19:40:48 +08:00
|
|
|
0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS;
|
2015-01-21 00:10:51 +08:00
|
|
|
|
|
|
|
|
// Branch on Bit Set /+32
|
2015-11-27 00:35:41 +08:00
|
|
|
def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
|
2016-03-24 19:40:48 +08:00
|
|
|
uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS;
|
2015-11-27 00:35:41 +08:00
|
|
|
def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
|
2016-03-24 19:40:48 +08:00
|
|
|
0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
|
2015-01-21 00:10:51 +08:00
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
// Multiply Doubleword to GPR
|
|
|
|
|
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
|
2016-03-24 19:40:48 +08:00
|
|
|
ADD_FM<0x1c, 0x03>, ASE_CNMIPS {
|
|
|
|
|
let Defs = [HI0, LO0, P0, P1, P2];
|
|
|
|
|
}
|
2014-03-20 19:51:58 +08:00
|
|
|
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
// Extract a signed bit field /+32
|
|
|
|
|
def EXTS : ExtsCins<"exts", II_EXT, GPR64Opnd, immZExt5>, EXTS_FM<0x3a>,
|
|
|
|
|
ASE_MIPS64_CNMIPS;
|
|
|
|
|
def EXTS32: ExtsCins<"exts32", II_EXT, GPR64Opnd, immZExt5Plus32>,
|
|
|
|
|
EXTS_FM<0x3b>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
|
|
|
|
|
// Clear and insert a bit field /+32
|
|
|
|
|
def CINS : ExtsCins<"cins", II_INS, GPR64Opnd, immZExt5, MipsCIns>,
|
|
|
|
|
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def CINS32: ExtsCins<"cins32", II_INS, GPR64Opnd, immZExt5Plus32, MipsCIns>,
|
|
|
|
|
EXTS_FM<0x33>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
let isCodeGenOnly = 1 in {
|
|
|
|
|
def CINS_i32 : ExtsCins<"cins", II_INS, GPR32Opnd, immZExt5, MipsCIns>,
|
|
|
|
|
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def CINS64_32 :InstSE<(outs GPR64Opnd:$rt),
|
|
|
|
|
(ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
|
|
|
|
|
"cins\t$rt, $rs, $pos, $lenm1", [], II_INS, FrmR,
|
|
|
|
|
"cins">,
|
|
|
|
|
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
}
|
|
|
|
|
}
|
2014-04-03 02:40:43 +08:00
|
|
|
|
2014-04-02 02:35:26 +08:00
|
|
|
// Move to multiplier/product register
|
2016-03-24 19:40:48 +08:00
|
|
|
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS;
|
|
|
|
|
def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS;
|
|
|
|
|
def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS;
|
2014-04-02 02:35:26 +08:00
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
// Count Ones in a Word/Doubleword
|
2016-03-24 19:40:48 +08:00
|
|
|
def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS;
|
|
|
|
|
def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS;
|
2014-03-20 19:51:58 +08:00
|
|
|
|
|
|
|
|
// Set on equal/not equal
|
2016-03-24 19:40:48 +08:00
|
|
|
def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS;
|
|
|
|
|
def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS;
|
|
|
|
|
def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS;
|
|
|
|
|
def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS;
|
2014-04-05 00:21:59 +08:00
|
|
|
|
2014-04-25 00:31:10 +08:00
|
|
|
// 192-bit x 64-bit Unsigned Multiply and Add
|
2016-03-24 19:40:48 +08:00
|
|
|
def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>,
|
|
|
|
|
ASE_CNMIPS {
|
|
|
|
|
let Defs = [P0, P1, P2];
|
|
|
|
|
}
|
2014-04-05 00:21:59 +08:00
|
|
|
|
|
|
|
|
// 64-bit Unsigned Multiply and Add Move
|
2016-03-24 19:40:48 +08:00
|
|
|
def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>,
|
|
|
|
|
ASE_CNMIPS {
|
|
|
|
|
let Defs = [MPL0, P0, P1, P2];
|
|
|
|
|
}
|
2014-04-05 00:21:59 +08:00
|
|
|
|
|
|
|
|
// 64-bit Unsigned Multiply and Add
|
2016-03-24 19:40:48 +08:00
|
|
|
def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>,
|
|
|
|
|
ASE_CNMIPS {
|
|
|
|
|
let Defs = [MPL1, MPL2, P0, P1, P2];
|
|
|
|
|
}
|
2014-04-05 00:21:59 +08:00
|
|
|
|
2015-05-29 00:23:16 +08:00
|
|
|
// Move between CPU and coprocessor registers
|
2016-08-24 21:00:47 +08:00
|
|
|
def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>,
|
|
|
|
|
ASE_CNMIPS;
|
2014-03-20 19:51:58 +08:00
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
}
|
2014-04-03 02:40:43 +08:00
|
|
|
|
2015-02-24 19:52:19 +08:00
|
|
|
/// Move between CPU and coprocessor registers
|
|
|
|
|
let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
|
2016-06-14 17:35:29 +08:00
|
|
|
def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, MFC3OP_FM<0x10, 1>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, MFC3OP_FM<0x10, 5>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, MFC3OP_FM<0x12, 1>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>,
|
|
|
|
|
ISA_MIPS3;
|
2015-02-24 19:52:19 +08:00
|
|
|
}
|
|
|
|
|
|
2011-10-01 02:51:46 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Arbitrary patterns that map to one or more instructions
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2016-07-25 17:57:28 +08:00
|
|
|
// Materialize i64 constants.
|
|
|
|
|
defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(i64 immZExt32Low16Zero:$imm),
|
|
|
|
|
(DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(i64 immZExt32:$imm),
|
|
|
|
|
(ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16),
|
|
|
|
|
(LO16 imm:$imm))>;
|
|
|
|
|
|
2011-11-15 03:06:14 +08:00
|
|
|
// extended loads
|
2014-04-30 00:24:10 +08:00
|
|
|
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
|
2011-10-11 08:55:05 +08:00
|
|
|
|
|
|
|
|
// hi/lo relocs
|
2017-01-27 19:36:52 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in
|
|
|
|
|
defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>;
|
|
|
|
|
|
|
|
|
|
multiclass MipsHighestHigherHiLoRelocs<Instruction Lui, Instruction Daddiu> {
|
|
|
|
|
def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)),
|
|
|
|
|
(JAL texternalsym:$dst)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
|
|
|
|
|
(Lui tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 tblockaddress:$in)),
|
|
|
|
|
(Lui tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 tjumptable:$in)),
|
|
|
|
|
(Lui tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 tconstpool:$in)),
|
|
|
|
|
(Lui tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)),
|
|
|
|
|
(Lui tglobaltlsaddr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHighest (i64 texternalsym:$in)),
|
|
|
|
|
(Lui texternalsym:$in)>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
|
|
|
|
|
(Daddiu ZERO_64, tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 tblockaddress:$in)),
|
|
|
|
|
(Daddiu ZERO_64, tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 tjumptable:$in)),
|
|
|
|
|
(Daddiu ZERO_64, tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 tconstpool:$in)),
|
|
|
|
|
(Daddiu ZERO_64, tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)),
|
|
|
|
|
(Daddiu ZERO_64, tglobaltlsaddr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHigher (i64 texternalsym:$in)),
|
|
|
|
|
(Daddiu ZERO_64, texternalsym:$in)>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tblockaddress:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tjumptable:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tconstpool:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tblockaddress:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tjumptable:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tconstpool:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
|
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tblockaddress:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tjumptable:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tconstpool:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
|
|
|
|
|
(Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// highest/higher/hi/lo relocs
|
|
|
|
|
let AdditionalPredicates = [NotInMicroMips] in
|
|
|
|
|
defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
|
|
|
|
|
|
2017-08-11 22:36:05 +08:00
|
|
|
// gp_rel relocs
|
|
|
|
|
def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
|
|
|
|
|
(DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64;
|
|
|
|
|
def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)),
|
|
|
|
|
(DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64;
|
|
|
|
|
|
2017-01-27 19:36:52 +08:00
|
|
|
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tconstpool, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<texternalsym, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tblockaddress, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tjumptable, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
|
2012-06-15 05:03:23 +08:00
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
|
2016-07-22 15:18:33 +08:00
|
|
|
defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
2016-03-02 04:25:43 +08:00
|
|
|
ZERO_64>;
|
|
|
|
|
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
|
2013-05-22 01:13:47 +08:00
|
|
|
(BLEZ64 i64:$lhs, bb:$dst)>;
|
2016-03-02 04:25:43 +08:00
|
|
|
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
|
2013-05-22 01:13:47 +08:00
|
|
|
(BGEZ64 i64:$lhs, bb:$dst)>;
|
|
|
|
|
|
2011-10-12 02:53:46 +08:00
|
|
|
// setcc patterns
|
2016-07-22 15:18:33 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
|
|
|
|
|
defm : SetlePats<GPR64, XORi, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgtPats<GPR64, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgePats<GPR64, XORi, SLT64, SLTu64>;
|
|
|
|
|
defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>;
|
|
|
|
|
}
|
2011-11-08 02:57:41 +08:00
|
|
|
// truncate
|
2014-11-08 00:54:21 +08:00
|
|
|
def : MipsPat<(trunc (assertsext GPR64:$src)),
|
|
|
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
2016-04-13 23:07:45 +08:00
|
|
|
// The forward compatibility strategy employed by MIPS requires us to treat
|
|
|
|
|
// values as being sign extended to an infinite number of bits. This allows
|
|
|
|
|
// existing software to run without modification on any future MIPS
|
|
|
|
|
// implementation (e.g. 128-bit, or 1024-bit). Being compatible with this
|
|
|
|
|
// strategy requires that truncation acts as a sign-extension for values being
|
|
|
|
|
// fed into instructions operating on 32-bit values. Such instructions have
|
|
|
|
|
// undefined results if this is not true.
|
|
|
|
|
// For our case, this means that we can't issue an extract_subreg for nodes
|
|
|
|
|
// such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the
|
|
|
|
|
// lower subreg would not be replicated into the upper half.
|
|
|
|
|
def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)),
|
2014-11-08 00:54:21 +08:00
|
|
|
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def : MipsPat<(i32 (trunc GPR64:$src)),
|
2014-05-07 18:27:09 +08:00
|
|
|
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
|
2012-02-28 15:46:26 +08:00
|
|
|
|
2015-04-21 18:49:03 +08:00
|
|
|
// variable shift instructions patterns
|
|
|
|
|
def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
2016-06-16 15:06:25 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
|
|
|
|
|
(DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
|
|
|
|
|
}
|
2015-04-21 18:49:03 +08:00
|
|
|
|
2011-12-08 07:14:41 +08:00
|
|
|
// 32-to-64-bit extension
|
2016-02-29 23:58:12 +08:00
|
|
|
def : MipsPat<(i64 (anyext GPR32:$src)),
|
|
|
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
|
|
|
|
|
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
|
2011-12-21 06:06:20 +08:00
|
|
|
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def : MipsPat<(i64 (zext GPR32:$src)), (DEXT64_32 GPR32:$src, 0, 32)>,
|
|
|
|
|
ISA_MIPS64R2;
|
|
|
|
|
def : MipsPat<(i64 (zext (i32 (shl GPR32:$rt, immZExt5:$imm)))),
|
|
|
|
|
(CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>,
|
|
|
|
|
ASE_MIPS64_CNMIPS;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-21 06:40:40 +08:00
|
|
|
// Sign extend in register
|
2013-08-07 07:08:38 +08:00
|
|
|
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
|
|
|
|
|
(SLL64_64 GPR64:$src)>;
|
2011-12-21 06:40:40 +08:00
|
|
|
|
2012-06-15 05:03:23 +08:00
|
|
|
// bswap MipsPattern
|
2013-08-07 07:08:38 +08:00
|
|
|
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
|
2012-10-10 00:27:43 +08:00
|
|
|
|
2015-01-26 20:33:22 +08:00
|
|
|
// Carry pattern
|
2016-04-08 15:27:26 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
2016-04-27 19:31:44 +08:00
|
|
|
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
|
|
|
|
|
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
|
2015-01-26 20:33:22 +08:00
|
|
|
def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
|
2016-04-08 15:27:26 +08:00
|
|
|
(DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;
|
2015-01-26 20:33:22 +08:00
|
|
|
def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
|
2016-04-08 15:27:26 +08:00
|
|
|
(DADDiu GPR64:$lhs, imm:$imm)>, ASE_NOT_DSP;
|
2015-01-26 20:33:22 +08:00
|
|
|
}
|
|
|
|
|
|
2015-01-21 00:10:51 +08:00
|
|
|
// Octeon bbit0/bbit1 MipsPattern
|
2016-03-02 04:25:43 +08:00
|
|
|
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
|
2016-03-24 19:40:48 +08:00
|
|
|
(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
2016-03-02 04:25:43 +08:00
|
|
|
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
|
2016-03-24 19:40:48 +08:00
|
|
|
(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
2016-03-02 04:25:43 +08:00
|
|
|
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
|
2016-03-24 19:40:48 +08:00
|
|
|
(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
2016-03-02 04:25:43 +08:00
|
|
|
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
|
2016-03-24 19:40:48 +08:00
|
|
|
(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
2017-08-30 19:25:38 +08:00
|
|
|
def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
|
|
|
|
|
(Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
|
|
|
|
|
(BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
|
|
|
|
|
(Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
|
2015-01-21 00:10:51 +08:00
|
|
|
|
2015-11-06 20:07:20 +08:00
|
|
|
// Atomic load patterns.
|
|
|
|
|
def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
|
|
|
|
|
|
|
|
|
|
// Atomic store patterns.
|
|
|
|
|
def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
|
|
|
|
|
def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
|
|
|
|
|
|
2012-10-10 00:27:43 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Instruction aliases
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
2016-04-08 15:27:26 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def : MipsInstAlias<"move $dst, $src",
|
|
|
|
|
(OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
|
|
|
|
GPR_64;
|
|
|
|
|
def : MipsInstAlias<"move $dst, $src",
|
|
|
|
|
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
|
|
|
|
|
GPR_64;
|
|
|
|
|
def : MipsInstAlias<"dadd $rs, $rt, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def : MipsInstAlias<"dadd $rs, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def : MipsInstAlias<"daddu $rs, $rt, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
|
|
|
|
|
0>, ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"daddu $rs, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
|
|
|
|
|
0>, ISA_MIPS3;
|
2017-02-24 22:34:32 +08:00
|
|
|
|
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi64, GPR64Opnd, imm64>,
|
|
|
|
|
GPR_64;
|
|
|
|
|
|
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi64, GPR64Opnd, imm64>,
|
|
|
|
|
GPR_64;
|
|
|
|
|
|
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi64, GPR64Opnd, imm64>,
|
|
|
|
|
GPR_64;
|
2016-04-08 15:27:26 +08:00
|
|
|
}
|
2016-04-27 19:31:44 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def : MipsInstAlias<"dneg $rt, $rs",
|
|
|
|
|
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dneg $rt",
|
2016-07-26 17:13:46 +08:00
|
|
|
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
|
2016-04-27 19:31:44 +08:00
|
|
|
ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dnegu $rt, $rs",
|
|
|
|
|
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
|
|
|
|
|
ISA_MIPS3;
|
2016-07-26 17:13:46 +08:00
|
|
|
def : MipsInstAlias<"dnegu $rt",
|
|
|
|
|
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
|
|
|
|
|
ISA_MIPS3;
|
2016-04-27 19:31:44 +08:00
|
|
|
}
|
2014-06-13 20:49:06 +08:00
|
|
|
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
|
|
|
InvertedImOperand64:$imm),
|
|
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def : MipsInstAlias<"dsubi $rs, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
|
|
InvertedImOperand64:$imm),
|
|
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
|
|
|
|
def : MipsInstAlias<"dsub $rs, $rt, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
|
|
|
|
|
InvertedImOperand64:$imm),
|
|
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
2014-05-09 00:12:31 +08:00
|
|
|
def : MipsInstAlias<"dsub $rs, $imm",
|
|
|
|
|
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
|
|
InvertedImOperand64:$imm),
|
2014-06-13 20:49:06 +08:00
|
|
|
0>, ISA_MIPS3_NOT_32R6_64R6;
|
2016-04-08 15:27:26 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
|
|
|
|
def : MipsInstAlias<"dsubu $rt, $rs, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
|
|
|
|
|
InvertedImOperand64:$imm), 0>, ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dsubu $rs, $imm",
|
|
|
|
|
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
|
|
|
|
|
InvertedImOperand64:$imm), 0>, ISA_MIPS3;
|
|
|
|
|
}
|
2014-05-09 17:24:49 +08:00
|
|
|
def : MipsInstAlias<"dsra $rd, $rt, $rs",
|
2014-05-09 21:02:27 +08:00
|
|
|
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
|
|
ISA_MIPS3;
|
2016-06-27 16:23:28 +08:00
|
|
|
let AdditionalPredicates = [NotInMicroMips] in {
|
2017-06-27 21:35:17 +08:00
|
|
|
def : MipsInstAlias<"dsll $rd, $rt, $rs",
|
|
|
|
|
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
|
|
ISA_MIPS3;
|
2016-06-27 16:23:28 +08:00
|
|
|
def : MipsInstAlias<"dsrl $rd, $rt, $rs",
|
|
|
|
|
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
|
|
|
|
ISA_MIPS3;
|
2017-06-27 21:35:17 +08:00
|
|
|
def : MipsInstAlias<"dsrl $rd, $rt",
|
|
|
|
|
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
|
|
|
|
ISA_MIPS3;
|
|
|
|
|
def : MipsInstAlias<"dsll $rd, $rt",
|
|
|
|
|
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
|
|
|
|
ISA_MIPS3;
|
2017-09-14 23:17:50 +08:00
|
|
|
def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
|
|
|
|
|
(DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
|
|
|
|
|
uimm_range_2_64:$size), 0>, ISA_MIPS64R2;
|
|
|
|
|
def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
|
|
|
|
|
(DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
|
|
|
|
|
uimm5_plus1:$size), 0>, ISA_MIPS64R2;
|
2013-01-19 04:15:06 +08:00
|
|
|
|
2012-10-11 18:21:34 +08:00
|
|
|
// Two operand (implicit 0 selector) versions:
|
2016-03-24 16:02:09 +08:00
|
|
|
def : MipsInstAlias<"dmtc0 $rt, $rd",
|
|
|
|
|
(DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
|
2016-03-31 16:51:24 +08:00
|
|
|
def : MipsInstAlias<"dmfc0 $rt, $rd",
|
|
|
|
|
(DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
|
2016-03-24 16:02:09 +08:00
|
|
|
}
|
2015-06-27 23:39:19 +08:00
|
|
|
def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
|
|
|
|
|
def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
|
2012-10-11 18:21:34 +08:00
|
|
|
|
2016-03-24 19:40:48 +08:00
|
|
|
def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS;
|
|
|
|
|
def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS;
|
2015-02-24 19:52:19 +08:00
|
|
|
|
2015-11-27 00:35:41 +08:00
|
|
|
// cnMIPS Aliases.
|
|
|
|
|
|
|
|
|
|
// bbit* with $p 32-63 converted to bbit*32 with $p 0-31
|
|
|
|
|
def : MipsInstAlias<"bbit0 $rs, $p, $offset",
|
|
|
|
|
(BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p,
|
|
|
|
|
brtarget:$offset), 0>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
def : MipsInstAlias<"bbit1 $rs, $p, $offset",
|
|
|
|
|
(BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p,
|
|
|
|
|
brtarget:$offset), 0>,
|
|
|
|
|
ASE_CNMIPS;
|
|
|
|
|
|
|
|
|
|
// exts with $pos 32-63 in converted to exts32 with $pos 0-31
|
|
|
|
|
def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1",
|
|
|
|
|
(EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs,
|
|
|
|
|
uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
ASE_MIPS64_CNMIPS;
|
2015-11-27 00:35:41 +08:00
|
|
|
def : MipsInstAlias<"exts $rt, $pos, $lenm1",
|
|
|
|
|
(EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt,
|
|
|
|
|
uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
|
|
|
ASE_MIPS64_CNMIPS;
|
2015-11-27 00:35:41 +08:00
|
|
|
|
|
|
|
|
// cins with $pos 32-63 in converted to cins32 with $pos 0-31
|
|
|
|
|
def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1",
|
|
|
|
|
(CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs,
|
|
|
|
|
uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
|
[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
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ASE_MIPS64_CNMIPS;
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2015-11-27 00:35:41 +08:00
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def : MipsInstAlias<"cins $rt, $pos, $lenm1",
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(CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt,
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uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>,
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[Mips] Add support to match more patterns for DEXT and CINS
This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.
For example, for the following:
define i64 @dext_and32(i64 zeroext %a) {
entry:
%and = and i64 %a, 4294967295
ret i64 %and
}
instead of generating:
0000000000000088 <dext_and32>:
88: 64010001 daddiu at,zero,1
8c: 0001083c dsll32 at,at,0x0
90: 6421ffff daddiu at,at,-1
94: 03e00008 jr ra
98: 00811024 and v0,a0,at
9c: 00000000 nop
the following gets generated:
0000000000000068 <dext_and32>:
68: 03e00008 jr ra
6c: 7c82f803 dext v0,a0,0x0,0x20
Cases that are covered:
DEXT:
1. and $src, mask where mask > 0xffff
2. zext $src zero extend from i32 to i64
CINS:
1. and (shl $src, pos), mask
2. shl (and $src, mask), pos
3. zext (shl $src, pos) zero extend from i32 to i64
Patch by Violeta Vukobrat.
Differential Revision: https://reviews.llvm.org/D30464
llvm-svn: 297832
2017-03-15 21:10:08 +08:00
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ASE_MIPS64_CNMIPS;
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2015-11-27 00:35:41 +08:00
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2015-02-24 19:52:19 +08:00
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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2015-03-04 21:01:14 +08:00
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class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
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2015-02-24 19:52:19 +08:00
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MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
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!strconcat(instr_asm, "\t$rt, $imm64")> ;
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2015-03-04 21:01:14 +08:00
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def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;
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2015-08-17 18:11:55 +08:00
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def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr),
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"dla\t$rt, $addr">;
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def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64),
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"dla\t$rt, $imm64">;
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2017-02-09 00:25:05 +08:00
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def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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simm32_relaxed:$imm),
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"dmul\t$rs, $rt, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmulo\t$rs, $rt, $rd">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmulou\t$rs, $rt, $rd">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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GPR64Opnd:$rd),
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"dmul\t$rs, $rt, $rd"> {
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let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips];
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}
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2017-02-14 00:06:48 +08:00
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let AdditionalPredicates = [NotInMicroMips] in {
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def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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"ddiv\t$rd, $rs, $rt">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"ddiv\t$rd, $rs, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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"ddivu\t$rd, $rs, $rt">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"ddivu\t$rd, $rs, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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// GAS expands 'div' and 'ddiv' differently when the destination
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// register is $zero and the instruction is in the two operand
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// form. 'ddiv' gets expanded, while 'div' is not expanded.
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def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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GPR64Opnd:$rt), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
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GPR64Opnd:$rd,
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imm64:$imm), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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// GAS expands 'divu' and 'ddivu' differently when the destination
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// register is $zero and the instruction is in the two operand
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// form. 'ddivu' gets expanded, while 'divu' is not expanded.
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def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt,
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GPR64Opnd:$rt,
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GPR64Opnd:$rs), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd,
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GPR64Opnd:$rd,
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imm64:$imm), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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}
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2017-02-28 23:55:23 +08:00
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def NORImm64 : NORIMM_DESC_BASE<GPR64Opnd, imm64>, GPR_64;
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def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
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imm64:$imm)>, GPR_64;
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def SLTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs),
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(ins GPR64Opnd:$rt, imm64:$imm),
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"slt\t$rs, $rt, $imm">, GPR_64;
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def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
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imm64:$imm)>, GPR_64;
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def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs),
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(ins GPR64Opnd:$rt, imm64:$imm),
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"sltu\t$rs, $rt, $imm">, GPR_64;
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def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
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imm64:$imm)>, GPR_64;
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