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llvm-project/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll

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ARM: yet another round of ARM test clean ups llvm-svn: 205586
2014-04-04 07:47:24 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
Add Thumb2 movcc instructions. llvm-svn: 74946
2009-07-08 04:39:03 +08:00
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
Convert to FileCheck llvm-svn: 89007
2009-11-17 08:20:26 +08:00
; CHECK: t1
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-18 04:13:28 +08:00
; CHECK: mvn r0, #-2147483648
Convert to FileCheck llvm-svn: 89007
2009-11-17 08:20:26 +08:00
; CHECK: cmp r2, #10
Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
2012-08-17 07:21:55 +08:00
; CHECK: it le
Use predication instead of pseudo-opcodes when folding into MOVCC. Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
2012-09-06 07:58:02 +08:00
; CHECK: addle r1, r0
Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
2012-08-17 07:21:55 +08:00
; CHECK: mov r0, r1
Add Thumb2 movcc instructions. llvm-svn: 74946
2009-07-08 04:39:03 +08:00
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
%tmp3 = add i32 %tmp2, %b
ret i32 %tmp3
}
define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
Convert to FileCheck llvm-svn: 89007
2009-11-17 08:20:26 +08:00
; CHECK: t2
; CHECK: cmp r2, #10
Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
2012-08-17 07:21:55 +08:00
; CHECK: it le
; CHECK: addle.w r1, r1, #-2147483648
; CHECK: mov r0, r1
Convert to FileCheck llvm-svn: 89007
2009-11-17 08:20:26 +08:00
Add Thumb2 movcc instructions. llvm-svn: 74946
2009-07-08 04:39:03 +08:00
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 2147483648
%tmp3 = add i32 %tmp2, %b
ret i32 %tmp3
}
define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
Convert to FileCheck llvm-svn: 89007
2009-11-17 08:20:26 +08:00
; CHECK: t3
; CHECK: cmp r2, #10
Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
2012-08-17 07:21:55 +08:00
; CHECK: it le
Use predication instead of pseudo-opcodes when folding into MOVCC. Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
2012-09-06 07:58:02 +08:00
; CHECK: suble r1, #10
Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
2012-08-17 07:21:55 +08:00
; CHECK: mov r0, r1
Add Thumb2 movcc instructions. llvm-svn: 74946
2009-07-08 04:39:03 +08:00
%tmp1 = icmp sgt i32 %c, 10
%tmp2 = select i1 %tmp1, i32 0, i32 10
%tmp3 = sub i32 %b, %tmp2
ret i32 %tmp3
}