2016-08-04 02:17:35 +08:00
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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2008-02-19 16:07:33 +08:00
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2010-08-02 08:18:19 +08:00
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define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
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2015-02-28 05:17:42 +08:00
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%tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
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2008-02-19 16:07:33 +08:00
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%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp4, <4 x i32>* %P1
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2015-02-28 05:17:42 +08:00
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%tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
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2008-02-19 16:07:33 +08:00
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%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp9, <4 x i32>* %P2
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2015-02-28 05:17:42 +08:00
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%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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2008-02-19 16:07:33 +08:00
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%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp13, <4 x float>* %P3
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ret void
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test1:
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2013-02-04 23:52:32 +08:00
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; CHECK-NOT: CPI
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2006-04-13 03:04:27 +08:00
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}
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2010-08-02 08:18:19 +08:00
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define <4 x i32> @test_30() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_30:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltisw
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; CHECK-NEXT: vadduwm
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; CHECK-NEXT: blr
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2006-04-17 13:58:22 +08:00
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}
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2006-04-17 14:06:50 +08:00
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2010-08-02 08:18:19 +08:00
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define <4 x i32> @test_29() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_29:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltisw
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; CHECK-NEXT: vspltisw
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; CHECK-NEXT: vsubuwm
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; CHECK-NEXT: blr
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2006-04-17 14:06:50 +08:00
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}
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2006-04-17 14:58:16 +08:00
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2010-08-02 08:18:19 +08:00
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define <8 x i16> @test_n30() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_n30:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltish
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; CHECK-NEXT: vadduhm
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; CHECK-NEXT: blr
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2006-04-17 14:58:16 +08:00
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}
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2010-08-02 08:18:19 +08:00
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define <16 x i8> @test_n104() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_n104:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltisb
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; CHECK-NEXT: vslb
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; CHECK-NEXT: blr
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2006-04-17 14:58:16 +08:00
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}
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2006-04-18 01:54:18 +08:00
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2010-08-02 08:18:19 +08:00
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define <4 x i32> @test_vsldoi() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_vsldoi:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltisw
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; CHECK-NEXT: vsldoi
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; CHECK-NEXT: blr
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2006-04-18 01:54:18 +08:00
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}
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2010-08-02 08:18:19 +08:00
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define <8 x i16> @test_vsldoi_65023() nounwind {
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ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_vsldoi_65023:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltish
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; CHECK-NEXT: vsldoi
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; CHECK-NEXT: blr
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2010-08-02 08:18:19 +08:00
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}
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define <4 x i32> @test_rol() nounwind {
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2008-02-19 16:07:33 +08:00
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ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
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2013-02-04 23:52:32 +08:00
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2013-07-14 04:38:47 +08:00
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; CHECK-LABEL: test_rol:
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2013-02-04 23:52:32 +08:00
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; CHECK: vspltisw
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; CHECK-NEXT: vrlw
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; CHECK-NEXT: blr
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2006-04-18 01:54:18 +08:00
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}
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