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llvm-project/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll

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[PowerPC] Eliminate integer compare instructions - vol. 1 This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 llvm-svn: 302810
2017-05-12 00:54:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: rldicr r3, r3, 58, 0
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: rldicr r3, r3, 58, 0
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: rldicr r3, r3, 58, 0
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicr r3, r3, 58, 0
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}