2017-06-02 16:53:19 +08:00
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; CHECK: ********** MI Scheduling **********
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; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
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; CHECK: ********** MI Scheduling **********
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; CHECK: schedule starting
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; CHECK: VSTMDIA_UPD
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 4
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; CHECK: Successors:
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2017-07-12 23:30:59 +08:00
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; CHECK: Data
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2017-06-02 16:53:19 +08:00
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; CHECK-SAME: Latency=1
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@a = global double 0.0, align 4
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@b = global double 0.0, align 4
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@c = global double 0.0, align 4
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define i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize {
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%vp2 = getelementptr double, double* %vptr, i32 1
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%vp3 = getelementptr double, double* %vptr, i32 2
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%v1 = load double, double* %vptr, align 8
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%v2 = load double, double* %vp2, align 8
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%v3 = load double, double* %vp3, align 8
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store double %v1, double* @a, align 8
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store double %v2, double* @b, align 8
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store double %v3, double* @c, align 8
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%ptr_after = getelementptr double, double* @a, i32 3
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%ptr_new_ival = ptrtoint double* %ptr_after to i32
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%ptr_new = inttoptr i32 %ptr_new_ival to i32*
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store i32 %ptr_new_ival, i32* %iptr, align 8
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%mul1 = mul i32 %ptr_new_ival, %iv1
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ret i32 %mul1
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}
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