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llvm-project/llvm/test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll

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Fix line-endings. NFCI. llvm-svn: 342639
2018-09-20 18:59:08 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64
define i16 @test_shl_i4(i16 %v, i16 %a, i16 %b) {
[GlobalISel][Legalizer] Widening the second src op of shifts bug fix The second source operand of G_SHL, G_ASHR, and G_LSHR must preserve its value as a (small) unsigned integer, therefore its incorrect to widen it in any way but by zero extending it. G_SHL was using G_ANYEXT and G_ASHR - G_SEXT (which is correct for their destination and first source operands, but not the "number of bits to shift" operand). Generally, shifts aren't as similar to regular binary operations as it might seem, for instance, they aren't commutative nor associative and the second source operand usually requires a special treatment. Reviewers: bogner, javed.absar, aivchenk, rovka Reviewed By: bogner Subscribers: igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46413 llvm-svn: 331926
2018-05-10 05:43:30 +08:00
; Let's say the arguments are the following unsigned
; integers in two’s complement representation:
;
Fix line-endings. NFCI. llvm-svn: 342639
2018-09-20 18:59:08 +08:00
; %v: 77 (0000 0000 0100 1101)
; %a: 74 (0000 0000 0100 1010)
; %b: 72 (0000 0000 0100 1000)
; X64-LABEL: test_shl_i4:
; X64: # %bb.0:
[x86] allow 8-bit adds to be promoted by convertToThreeAddress() to form LEA This extends the code that handles 16-bit add promotion to form LEA to also allow 8-bit adds. That allows us to combine add ops with register moves and save some instructions. This is another step towards allowing add truncation in generic DAGCombiner (see D54640). Differential Revision: https://reviews.llvm.org/D55494 llvm-svn: 348946
2018-12-13 01:58:27 +08:00
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edx killed $edx def $rdx
; X64-NEXT: leal (%rdx,%rsi), %ecx
Fix line-endings. NFCI. llvm-svn: 342639
2018-09-20 18:59:08 +08:00
; X64-NEXT: andb $15, %cl
; X64-NEXT: # kill: def $cl killed $cl killed $ecx
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-15 05:02:02 +08:00
; X64-NEXT: shlb %cl, %dil
; X64-NEXT: movzbl %dil, %eax
Fix line-endings. NFCI. llvm-svn: 342639
2018-09-20 18:59:08 +08:00
; X64-NEXT: andw $15, %ax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
%v.t = trunc i16 %v to i4 ; %v.t: 13 (1101)
%a.t = trunc i16 %a to i4 ; %a.t: 10 (1010)
%b.t = trunc i16 %b to i4 ; %b.t: 8 (1000)
[GlobalISel][Legalizer] Widening the second src op of shifts bug fix The second source operand of G_SHL, G_ASHR, and G_LSHR must preserve its value as a (small) unsigned integer, therefore its incorrect to widen it in any way but by zero extending it. G_SHL was using G_ANYEXT and G_ASHR - G_SEXT (which is correct for their destination and first source operands, but not the "number of bits to shift" operand). Generally, shifts aren't as similar to regular binary operations as it might seem, for instance, they aren't commutative nor associative and the second source operand usually requires a special treatment. Reviewers: bogner, javed.absar, aivchenk, rovka Reviewed By: bogner Subscribers: igorb, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46413 llvm-svn: 331926
2018-05-10 05:43:30 +08:00
%n.t = add i4 %a.t, %b.t ; %n.t: 2 (0010)
%r.t = shl i4 %v.t, %n.t ; %r.t: 4 (0100)
%r = zext i4 %r.t to i16
Fix line-endings. NFCI. llvm-svn: 342639
2018-09-20 18:59:08 +08:00
; %r: 4 (0000 0000 0000 0100)
ret i16 %r
; %di: 77 (0000 0000 0100 1101)
; %si: 74 (0000 0000 0100 1010)
; %dx: 72 (0000 0000 0100 1000)
; %dx: 146 (0000 0000 1001 0010)
; %dx: 2 (0000 0000 0000 0010)
; %cx: 2 (0000 0000 0000 0010)
; %di: 52 (0000 0000 0011 0100)
; %di: 4 (0000 0000 0000 0100)
; %ax: 4 (0000 0000 0000 0100)
; Let's pretend that legalizing G_SHL by widening its second
; source operand is done via G_ANYEXT rather than G_ZEXT and
; see what happens:
; addb %sil, %dl
; %dx: 146 (0000 0000 1001 0010)
; movl %edx, %ecx
; %cx: 146 (0000 0000 1001 0010)
; shlb %cl, %dil
; %di: 0 (0000 0000 0000 0000)
; andw $15, %di
; %di: 0 (0000 0000 0000 0000)
; movl %edi, %eax
; %ax: 0 (0000 0000 0000 0000)
; retq
}