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llvm-project/llvm/test/CodeGen/X86/apm.ll

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[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X64
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,WIN64
Rewrite mwait and monitor support and custom lower arguments. Fixes PR8573. llvm-svn: 120404
2010-11-30 15:20:12 +08:00
; PR8573
define void @foo(i8* %P, i32 %E, i32 %H) nounwind {
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; X86-LABEL: foo:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
2019-04-04 07:28:30 +08:00
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; X86-NEXT: monitor
; X86-NEXT: retl
;
; X64-LABEL: foo:
; X64: # %bb.0: # %entry
; X64-NEXT: movl %esi, %ecx
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
2019-04-04 07:28:30 +08:00
; X64-NEXT: movq %rdi, %rax
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; X64-NEXT: monitor
; X64-NEXT: retq
;
; WIN64-LABEL: foo:
; WIN64: # %bb.0: # %entry
[X86] Remove CustomInserter pseudos for MONITOR/MONITORX/CLZERO. Use custom instruction selection instead. This custom inserter existed so we could do a weird thing where we pretended that the instructions support a full address mode instead of taking a pointer in EAX/RAX. I think was largely so we could be pointer size agnostic in the isel pattern. To make this work we would then put the address into an LEA into EAX/RAX in front of the instruction after isel. But the LEA is overkill when we just have a base pointer. So we end up using the LEA as a slower MOV instruction. With this change we now just do custom selection during isel instead and just assign the incoming address of the intrinsic into EAX/RAX based on its size. After the intrinsic is selected, we can let isel take care of selecting an LEA or other operation to do any address computation needed in this basic block. I've also split the instruction into a 32-bit mode version and a 64-bit mode version so the implicit use is properly sized based on the pointer. Without this we get comments in the assembly output about killing eax and defing rax or vice versa depending on whether we define the instruction to use EAX/RAX. llvm-svn: 357652
2019-04-04 07:28:30 +08:00
; WIN64-NEXT: movq %rcx, %rax
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; WIN64-NEXT: movl %edx, %ecx
; WIN64-NEXT: movl %r8d, %edx
; WIN64-NEXT: monitor
; WIN64-NEXT: retq
Rewrite mwait and monitor support and custom lower arguments. Fixes PR8573. llvm-svn: 120404
2010-11-30 15:20:12 +08:00
entry:
tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
ret void
}
declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
define void @bar(i32 %E, i32 %H) nounwind {
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; X86-LABEL: bar:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mwait
; X86-NEXT: retl
;
; X64-LABEL: bar:
; X64: # %bb.0: # %entry
; X64-NEXT: movl %esi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: movl %edi, %ecx
[X86][SSE3] Regenerate mwait/monitor intrinsic tests Added i686 checks llvm-svn: 329527
2018-04-08 20:29:11 +08:00
; X64-NEXT: mwait
; X64-NEXT: retq
;
; WIN64-LABEL: bar:
; WIN64: # %bb.0: # %entry
; WIN64-NEXT: movl %edx, %eax
; WIN64-NEXT: mwait
; WIN64-NEXT: retq
Rewrite mwait and monitor support and custom lower arguments. Fixes PR8573. llvm-svn: 120404
2010-11-30 15:20:12 +08:00
entry:
tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
ret void
}
declare void @llvm.x86.sse3.mwait(i32, i32) nounwind