2018-10-25 22:11:07 +08:00
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# RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -no-stack-coloring=false -run-pass stack-coloring -o - %s
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2018-05-29 21:52:24 +08:00
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# Test to insure that the liveness analysis in the StackColoring
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# pass gracefully handles statically unreachable blocks. See PR 37310.
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# This MIR testcase was created by compiling the following test, first
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# with "clang -emit-llvm -S" and then "llc -stop-before stack-coloring",
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# and finally editing the resulting MIR by hand to introduce a statically
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# unreachable BB (to wit: rename all bb.3 to bb.4, rename bb.2 to bb.3,
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# then add bb.2 with unconditional jump to bb.4).
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# Original C code:
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# extern int inita(int *);
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# void foo(int x) {
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# if (x != 3) {
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# int q[128];
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# inita(&q[0]);
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# return;
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# }
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# int r[128];
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# inita(&r[x]);
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# }
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--- |
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define void @foo(i32 %x) {
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entry:
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%q = alloca [128 x i32], align 16
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%r = alloca [128 x i32], align 16
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%cmp = icmp eq i32 %x, 3
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br i1 %cmp, label %if.end, label %if.then
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if.then: ; preds = %entry
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%0 = bitcast [128 x i32]* %q to i8*
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call void @llvm.lifetime.start.p0i8(i64 512, i8* nonnull %0)
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%arrayidx2 = bitcast [128 x i32]* %q to i32*
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%call = call i32 @inita(i32* nonnull %arrayidx2)
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call void @llvm.lifetime.end.p0i8(i64 512, i8* nonnull %0)
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br label %return
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unreachable:
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br label %return
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if.end: ; preds = %entry
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%1 = bitcast [128 x i32]* %r to i8*
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call void @llvm.lifetime.start.p0i8(i64 512, i8* nonnull %1)
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%arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32]* %r, i64 0, i64 3
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%call2 = call i32 @inita(i32* nonnull %arrayidx1)
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call void @llvm.lifetime.end.p0i8(i64 512, i8* nonnull %1)
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br label %return
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return: ; preds = %if.end, %if.then
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ret void
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}
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declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
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declare i32 @inita(i32*)
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declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
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declare void @llvm.stackprotector(i8*, i8**)
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...
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---
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name: foo
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr32, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr32, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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liveins:
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2018-10-25 07:52:33 +08:00
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- { reg: '$edi' }
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2018-05-29 21:52:24 +08:00
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 16
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adjustsStack: false
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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- { id: 0, name: q, type: default, offset: 0, size: 512, alignment: 16,
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2019-06-17 17:13:29 +08:00
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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2018-05-29 21:52:24 +08:00
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: r, type: default, offset: 0, size: 512, alignment: 16,
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2019-06-17 17:13:29 +08:00
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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2018-05-29 21:52:24 +08:00
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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constants:
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body: |
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bb.0.entry:
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successors: %bb.3(0x40000000), %bb.1(0x40000000)
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liveins: $edi
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%0:gr32 = COPY $edi
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%1:gr32 = SUB32ri8 %0, 3, implicit-def $eflags
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.3, 4, implicit $eflags
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2018-05-29 21:52:24 +08:00
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JMP_1 %bb.1
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bb.1.if.then:
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successors: %bb.4(0x80000000)
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LIFETIME_START %stack.0.q
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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%2:gr64 = LEA64r %stack.0.q, 1, $noreg, 0, $noreg
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$rdi = COPY %2
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CALL64pcrel32 @inita, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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%3:gr32 = COPY $eax
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LIFETIME_END %stack.0.q
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JMP_1 %bb.4
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bb.2.unreachable:
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successors: %bb.4(0x80000000)
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JMP_1 %bb.4
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bb.3.if.end:
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successors: %bb.4(0x80000000)
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LIFETIME_START %stack.1.r
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%4:gr64 = LEA64r %stack.1.r, 1, $noreg, 12, $noreg
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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$rdi = COPY %4
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CALL64pcrel32 @inita, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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%5:gr32 = COPY $eax
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LIFETIME_END %stack.1.r
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bb.4.return:
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RET 0
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...
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