forked from OSchip/llvm-project
216 lines
9.6 KiB
LLVM
216 lines
9.6 KiB
LLVM
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; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s
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;
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; void f(float a[100][100]) {
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; float x;
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;
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; for (int i = 0; i < 100; i++) {
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; for (int j = 0; j < 100; j++) {
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; for (int k = 0; k < 100; k++) {
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; if (k == 0)
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; x = 42;
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; a[i][j] += x;
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; x++;
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; }
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; }
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; }
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; }
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; The scop we generate for this kernel has a very large number of statements
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; and scalar data-dependences due to x being passed along as SSA value or PHI
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; node.
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; CHECK: Stmt_bb5
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; CHECK: Domain :=
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; CHECK: { Stmt_bb5[i0] : i0 <= 100 and i0 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb5[i0] -> [i0, 0, 0, 0, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb5[i0] -> MemRef_x_0__phi[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb5[i0] -> MemRef_x_0[] };
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; CHECK: Stmt_bb6
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; CHECK: Domain :=
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; CHECK: { Stmt_bb6[i0] : i0 <= 99 and i0 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb6[i0] -> [i0, 1, 0, 0, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb6[i0] -> MemRef_x_0[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb6[i0] -> MemRef_x_1__phi[] };
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; CHECK: Stmt_bb7
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; CHECK: Domain :=
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; CHECK: { Stmt_bb7[i0, i1] : i0 <= 99 and i0 >= 0 and i1 <= 100 and i1 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb7[i0, i1] -> [i0, 2, i1, 0, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb7[i0, i1] -> MemRef_x_1__phi[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb7[i0, i1] -> MemRef_x_1[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb7[i0, i1] -> MemRef_x_1_lcssa__phi[] };
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; CHECK: Stmt_bb8
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; CHECK: Domain :=
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; CHECK: { Stmt_bb8[i0, i1] : i1 <= 99 and i0 <= 99 and i0 >= 0 and i1 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb8[i0, i1] -> [i0, 2, i1, 1, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb8[i0, i1] -> MemRef_x_1[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb8[i0, i1] -> MemRef_x_2__phi[] };
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; CHECK: Stmt_bb9
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; CHECK: Domain :=
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; CHECK: { Stmt_bb9[i0, i1, i2] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 and i2 <= 100 and i2 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb9[i0, i1, i2] -> [i0, 2, i1, 2, i2, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb9[i0, i1, i2] -> MemRef_x_2__phi[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb9[i0, i1, i2] -> MemRef_x_2[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb9[i0, i1, i2] -> MemRef_x_2_lcssa__phi[] };
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; CHECK: Stmt_bb10
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; CHECK: Domain :=
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; CHECK: { Stmt_bb10[i0, i1, i2] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 and i2 <= 99 and i2 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb10[i0, i1, i2] -> [i0, 2, i1, 2, i2, 1] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb10[i0, i1, i2] -> MemRef_x_2[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb10[i0, i1, i2] -> MemRef_x_3__phi[] };
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; CHECK: Stmt_bb11
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; CHECK: Domain :=
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; CHECK: { Stmt_bb11[i0, i1, 0] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb11[i0, i1, i2] -> [i0, 2, i1, 2, 0, 2] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb11[i0, i1, i2] -> MemRef_x_3__phi[] };
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; CHECK: Stmt_bb12
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; CHECK: Domain :=
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; CHECK: { Stmt_bb12[i0, i1, i2] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 and i2 <= 99 and i2 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb12[i0, i1, i2] -> [i0, 2, i1, 2, i2, 3] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb12[i0, i1, i2] -> MemRef_x_3__phi[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb12[i0, i1, i2] -> MemRef_x_3[] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK: { Stmt_bb12[i0, i1, i2] -> MemRef_a[i0, i1] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK: { Stmt_bb12[i0, i1, i2] -> MemRef_a[i0, i1] };
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; CHECK: Stmt_bb16
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; CHECK: Domain :=
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; CHECK: { Stmt_bb16[i0, i1, i2] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 and i2 <= 99 and i2 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb16[i0, i1, i2] -> [i0, 2, i1, 2, i2, 4] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb16[i0, i1, i2] -> MemRef_x_2__phi[] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb16[i0, i1, i2] -> MemRef_x_3[] };
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; CHECK: Stmt_bb19
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; CHECK: Domain :=
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; CHECK: { Stmt_bb19[i0, i1] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb19[i0, i1] -> [i0, 2, i1, 3, 0, 0] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb19[i0, i1] -> MemRef_x_2_lcssa[] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb19[i0, i1] -> MemRef_x_2_lcssa__phi[] };
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; CHECK: Stmt_bb20
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; CHECK: Domain :=
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; CHECK: { Stmt_bb20[i0, i1] : i0 <= 99 and i0 >= 0 and i1 <= 99 and i1 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb20[i0, i1] -> [i0, 2, i1, 4, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb20[i0, i1] -> MemRef_x_2_lcssa[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb20[i0, i1] -> MemRef_x_1__phi[] };
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; CHECK: Stmt_bb21
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; CHECK: Domain :=
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; CHECK: { Stmt_bb21[i0] : i0 <= 99 and i0 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb21[i0] -> [i0, 3, 0, 0, 0, 0] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb21[i0] -> MemRef_x_1_lcssa[] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb21[i0] -> MemRef_x_1_lcssa__phi[] };
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; CHECK: Stmt_bb22
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; CHECK: Domain :=
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; CHECK: { Stmt_bb22[i0] : i0 <= 99 and i0 >= 0 };
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; CHECK: Schedule :=
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; CHECK: { Stmt_bb22[i0] -> [i0, 4, 0, 0, 0, 0] };
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; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb22[i0] -> MemRef_x_1_lcssa[] };
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; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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; CHECK: { Stmt_bb22[i0] -> MemRef_x_0__phi[] };
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f([100 x float]* %a) {
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bb:
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br label %bb5
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bb5: ; preds = %bb22, %bb
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%indvars.iv2 = phi i64 [ %indvars.iv.next3, %bb22 ], [ 0, %bb ]
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%x.0 = phi float [ undef, %bb ], [ %x.1.lcssa, %bb22 ]
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%exitcond4 = icmp ne i64 %indvars.iv2, 100
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br i1 %exitcond4, label %bb6, label %bb23
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bb6: ; preds = %bb5
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br label %bb7
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bb7: ; preds = %bb20, %bb6
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%indvars.iv = phi i64 [ %indvars.iv.next, %bb20 ], [ 0, %bb6 ]
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%x.1 = phi float [ %x.0, %bb6 ], [ %x.2.lcssa, %bb20 ]
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%exitcond1 = icmp ne i64 %indvars.iv, 100
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br i1 %exitcond1, label %bb8, label %bb21
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bb8: ; preds = %bb7
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br label %bb9
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bb9: ; preds = %bb16, %bb8
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%x.2 = phi float [ %x.1, %bb8 ], [ %tmp17, %bb16 ]
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%k.0 = phi i32 [ 0, %bb8 ], [ %tmp18, %bb16 ]
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%exitcond = icmp ne i32 %k.0, 100
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br i1 %exitcond, label %bb10, label %bb19
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bb10: ; preds = %bb9
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%tmp = icmp eq i32 %k.0, 0
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br i1 %tmp, label %bb11, label %bb12
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bb11: ; preds = %bb10
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br label %bb12
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bb12: ; preds = %bb11, %bb10
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%x.3 = phi float [ 4.200000e+01, %bb11 ], [ %x.2, %bb10 ]
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%tmp13 = getelementptr inbounds [100 x float], [100 x float]* %a, i64 %indvars.iv2, i64 %indvars.iv
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%tmp14 = load float, float* %tmp13, align 4
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%tmp15 = fadd float %tmp14, %x.3
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store float %tmp15, float* %tmp13, align 4
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br label %bb16
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bb16: ; preds = %bb12
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%tmp17 = fadd float %x.3, 1.000000e+00
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%tmp18 = add nuw nsw i32 %k.0, 1
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br label %bb9
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bb19: ; preds = %bb9
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%x.2.lcssa = phi float [ %x.2, %bb9 ]
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br label %bb20
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bb20: ; preds = %bb19
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %bb7
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bb21: ; preds = %bb7
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%x.1.lcssa = phi float [ %x.1, %bb7 ]
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br label %bb22
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bb22: ; preds = %bb21
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%indvars.iv.next3 = add nuw nsw i64 %indvars.iv2, 1
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br label %bb5
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bb23: ; preds = %bb5
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ret void
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}
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