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llvm-project/llvm/lib/Target/Mips/MipsCondMov.td

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remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
add Emacs tag and fix some comment error in file headers llvm-svn: 150775
2012-02-17 09:23:50 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is the Conditional Moves implementation.
//
//===----------------------------------------------------------------------===//
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
// Conditional moves:
// These instructions are expanded in
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions.
// cond:int, data:int
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
2013-07-16 18:07:14 +08:00
class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
[mips] Refactor conditional move instructions. llvm-svn: 171511
2013-01-05 03:16:38 +08:00
InstrItinClass Itin> :
InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. llvm-svn: 190148
2013-09-06 20:41:17 +08:00
!strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
let Constraints = "$F = $rd";
}
// cond:int, data:float
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
2013-07-16 18:07:14 +08:00
class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
InstrItinClass Itin> :
InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
!strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
HARDFLOAT {
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
let Constraints = "$F = $fd";
}
[mips] Delete all floating point instruction classes that are no longer used. No functionality change. llvm-svn: 170084
2012-12-13 10:05:02 +08:00
// cond:float, data:int
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
2013-07-16 18:07:14 +08:00
class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
SDPatternOperator OpNode = null_frag> :
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
[mips] Fix FP conditional move instructions to have explicit FP condition code register operands. llvm-svn: 187242
2013-07-27 04:51:20 +08:00
!strconcat(opstr, "\t$rd, $rs, $fcc"),
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
[(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
Itin, FrmFR, opstr>, HARDFLOAT {
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
let Constraints = "$F = $rd";
}
[mips] Delete all floating point instruction classes that are no longer used. No functionality change. llvm-svn: 170084
2012-12-13 10:05:02 +08:00
// cond:float, data:float
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
SDPatternOperator OpNode = null_frag> :
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
[mips] Fix FP conditional move instructions to have explicit FP condition code register operands. llvm-svn: 187242
2013-07-27 04:51:20 +08:00
!strconcat(opstr, "\t$fd, $fs, $fcc"),
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. llvm-svn: 187410
2013-07-30 18:12:14 +08:00
[(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
[mips] Add the SoftFloat MipsSubtarget feature. Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
2015-05-07 18:29:52 +08:00
Itin, FrmFR, opstr>, HARDFLOAT {
[mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080
2012-12-13 09:41:15 +08:00
let Constraints = "$F = $fd";
}
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
// select patterns
multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
Instruction MOVZInst, Instruction SLTOp,
Instruction SLTuOp, Instruction SLTiOp,
Instruction SLTiuOp> {
def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
DRC:$F)>;
}
multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
Instruction MOVZInst, Instruction XOROp> {
def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
}
multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
Instruction MOVZInst, Instruction XORiOp> {
def : MipsPat<
(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
(MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
}
multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
Instruction XOROp> {
def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
(MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
(MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
(MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
}
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
// Instantiation of instructions.
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
[mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements that were missed Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3548 llvm-svn: 207558
2014-04-30 01:04:30 +08:00
let isCodeGenOnly = 1 in {
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
2011-10-18 02:53:29 +08:00
}
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
[mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements that were missed Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3548 llvm-svn: 207558
2014-04-30 01:04:30 +08:00
let isCodeGenOnly = 1 in {
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
2011-10-18 02:53:29 +08:00
}
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
[mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC. Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
2016-06-15 18:36:16 +08:00
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
2011-10-18 02:53:29 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
[mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC. Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
2016-06-15 18:36:16 +08:00
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
II_MOVZ_D>, CMov_I_F_FM<18, 17>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
II_MOVN_D>, CMov_I_F_FM<19, 17>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
let DecoderNamespace = "Mips64" in {
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only. llvm-svn: 188690
2013-08-20 03:08:03 +08:00
let isCodeGenOnly = 1 in {
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only. llvm-svn: 188690
2013-08-20 03:08:03 +08:00
}
Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
2011-10-18 02:53:29 +08:00
}
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
[mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC. Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
2016-06-15 18:36:16 +08:00
CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
[mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC. Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
2016-06-15 18:36:16 +08:00
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. llvm-svn: 142226
2011-10-18 02:53:29 +08:00
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
[mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
2014-05-09 22:06:17 +08:00
MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only. llvm-svn: 188690
2013-08-20 03:08:03 +08:00
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
let DecoderNamespace = "Mips64" in {
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD] No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
2014-01-21 19:28:03 +08:00
def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
}
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
// Instantiation of conditional move patterns.
defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
Move class and instruction definitions for conditional moves to a seperate file. llvm-svn: 142220
2011-10-18 02:43:19 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
[mips] Promote the result of SETCC nodes to GPR width. Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
2016-03-01 18:08:01 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
GPR_64;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_32;
defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_32;
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
2014-05-07 22:25:43 +08:00
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64;
defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64;
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64;
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
[mips] Fix c.<cc>.<fmt> instruction definition. As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
2016-09-09 17:22:52 +08:00
multiclass FPSetccPats<Instruction MOVT, Instruction MOVF, dag ADD,
RegisterOperand RC> {
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setgt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setlt RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setle RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setoeq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setogt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setoge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setolt RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setole RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setone RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(seto RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setuo RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setueq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setugt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setult RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setule RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setune RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm S : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), FGR32Opnd>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm D32 : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), AFGR64Opnd>, FGR_32,
INSN_MIPS4_32_NOT_32R6_64R6;
defm D64 : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), FGR64Opnd>, FGR_64,
INSN_MIPS4_32_NOT_32R6_64R6;
}
multiclass FPSelectPats<RegisterOperand RC, RegisterOperand RO, string Type,
Instruction MOVT, Instruction MOVF> {
// Ordered
def : MipsPat<(select (i32 (setoeq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setogt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setoge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setolt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setole RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setone RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (seto RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UN_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
// Unordered
def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_UN_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setueq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setugt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setuge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setult RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_ULT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setule RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setune RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
// Unspecified ordering - treated as ordered.
def : MipsPat<(select (i32 (seteq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setgt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_LT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setlt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_LT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setle RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setne RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm : FPSelectPats<FGR32Opnd, FGR32Opnd, "S", MOVT_S, MOVF_S>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, AFGR64Opnd, "S", MOVT_D32, MOVF_D32>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, FGR64Opnd, "S", MOVT_D64, MOVF_D64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, AFGR64Opnd, "D32", MOVT_D32, MOVF_D32>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, FGR32Opnd, "D32", MOVT_S, MOVF_S>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, FGR64Opnd, "D64", MOVT_D64, MOVF_D64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, FGR32Opnd, "D64", MOVT_S, MOVF_S>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, GPR32Opnd, "S", MOVT_I, MOVF_I>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, GPR32Opnd, "D32", MOVT_I, MOVF_I>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, GPR32Opnd, "D64", MOVT_I, MOVF_I>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, GPR64Opnd,"S", MOVT_I64, MOVF_I64>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, GPR64Opnd, "D32", MOVT_I64, MOVF_I64>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, GPR64Opnd, "D64", MOVT_I64, MOVF_I64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
}
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
// For targets that don't have conditional-move instructions
// we have to match SELECT nodes with pseudo instructions.
let usesCustomInserter = 1 in {
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
class Select_Pseudo<RegisterOperand RC> :
[mips] Fix c.<cc>.<fmt> instruction definition. As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
2016-09-09 17:22:52 +08:00
PseudoSE<(outs RC:$dst), (ins RC:$T, GPR32Opnd:$cond, RC:$F),
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
[(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
ISA_MIPS1_NOT_4_32;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
class SelectFP_Pseudo_T<RegisterOperand RC> :
[mips] Fix c.<cc>.<fmt> instruction definition. As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
2016-09-09 17:22:52 +08:00
PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F),
[(set RC:$dst, (MipsCMovFP_T RC:$T, FCC:$cond, RC:$F))]>,
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
ISA_MIPS1_NOT_4_32;
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
class SelectFP_Pseudo_F<RegisterOperand RC> :
[mips] Fix c.<cc>.<fmt> instruction definition. As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
2016-09-09 17:22:52 +08:00
PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F),
[(set RC:$dst, (MipsCMovFP_F RC:$T, FCC:$cond, RC:$F))]>,
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
ISA_MIPS1_NOT_4_32;
}
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-02 04:25:43 +08:00
def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
[mips] Enable code generation for MIPS-III. Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
2014-12-12 23:16:46 +08:00
def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
[mips] Enable code generation for MIPS-III. Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
2014-12-12 23:16:46 +08:00
def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
[mips] Enable code generation for MIPS-III. Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
2014-12-12 23:16:46 +08:00
def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
[mips] Support SELECT nodes for targets that don't have conditional-move instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
2014-12-12 22:41:37 +08:00
def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
[mips] Enable code generation for MIPS-III. Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
2014-12-12 23:16:46 +08:00
def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;
[mips] Fix c.<cc>.<fmt> instruction definition. As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
2016-09-09 17:22:52 +08:00
let AdditionalPredicates = [NotInMicroMips] in {
defm : FPSelectPats<FGR32Opnd, FGR32Opnd, "S", PseudoSELECTFP_T_S,
PseudoSELECTFP_F_S>, ISA_MIPS1_NOT_4_32;
defm : FPSelectPats<AFGR64Opnd, AFGR64Opnd, "D32", PseudoSELECTFP_T_D32,
PseudoSELECTFP_F_D32>, FGR_32, ISA_MIPS1_NOT_4_32;
defm : FPSelectPats<FGR64Opnd, FGR64Opnd, "D64", PseudoSELECTFP_T_D64,
PseudoSELECTFP_F_D64>, FGR_64, ISA_MIPS1_NOT_4_32;
}