maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir

75 lines
2.6 KiB
Plaintext
Raw Normal View History

AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
# https://bugs.llvm.org/show_bug.cgi?id=33620
---
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
# This would assert due to the empty live interval created for %9
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
# on the last S_NOP with an undef subreg use.
# CHECK-LABEL: name: expecting_non_empty_interval
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec
[AMDGPU] Switch to the new addr space mapping by default This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
2018-02-03 00:07:16 +08:00
# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
# CHECK: S_NOP 0, implicit %6.sub1
[AMDGPU] Switch to the new addr space mapping by default This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
2018-02-03 00:07:16 +08:00
# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
# CHECK-NEXT: S_NOP 0, implicit %8.sub1
# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
name: expecting_non_empty_interval
tracksRegLiveness: true
MIR: Allow targets to serialize MachineFunctionInfo This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215
2019-03-15 06:54:43 +08:00
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
scratchWaveOffsetReg: $sgpr4
frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
body: |
bb.0:
successors: %bb.1
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $exec
undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $exec
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
bb.1:
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
S_NOP 0, implicit %2.sub1
RA: Remove assert on empty live intervals This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
2017-07-22 07:56:13 +08:00
S_NOP 0, implicit %0.sub1
S_NOP 0, implicit undef %0.sub0
...
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
# Similar assert which happens when trying to rematerialize.
# https://bugs.llvm.org/show_bug.cgi?id=33884
---
# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
# CHECK-NOT: MOV
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
# CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
# CHECK: bb.1:
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
# CHECK-NEXT: S_NOP 0, implicit %1.sub2
# CHECK-NEXT: S_NOP 0, implicit undef %4.sub0
# CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
# CHECK-NEXT: S_NOP 0, implicit %2.sub2
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
name: rematerialize_empty_interval_has_reference
tracksRegLiveness: true
MIR: Allow targets to serialize MachineFunctionInfo This has been a very painful missing feature that has made producing reduced testcases difficult. In particular the various registers determined for stack access during function lowering were necessary to avoid undefined register errors in a large percentage of cases. Implement a subset of the important fields that need to be preserved for AMDGPU. Most of the changes are to support targets parsing register fields and properly reporting errors. The biggest sort-of bug remaining is for fields that can be initialized from the IR section will be overwritten by a default initialized machineFunctionInfo section. Another remaining bug is the machineFunctionInfo section is still printed even if empty. llvm-svn: 356215
2019-03-15 06:54:43 +08:00
machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
scratchWaveOffsetReg: $sgpr4
frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
body: |
bb.0:
successors: %bb.1
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
bb.1:
AMDGPU: Cleanup / relax tests for future changes llvm-svn: 347576
2018-11-27 01:17:07 +08:00
S_NOP 0, implicit %1.sub2
RA: Remove another assert on empty intervals This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
2017-07-22 08:24:01 +08:00
S_NOP 0, implicit undef %0.sub0
S_NOP 0, implicit %0.sub2
...