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llvm-project/clang/test/CodeGen/RISCV/riscv-atomics.c

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[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
// RUN: %clang_cc1 -triple riscv32 -O1 -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32I
// RUN: %clang_cc1 -triple riscv32 -target-feature +a -O1 -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32IA
// RUN: %clang_cc1 -triple riscv64 -O1 -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64I
// RUN: %clang_cc1 -triple riscv64 -target-feature +a -O1 -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64IA
// This test demonstrates that MaxAtomicInlineWidth is set appropriately when
// the atomics instruction set extension is enabled.
#include <stdatomic.h>
#include <stdint.h>
void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) {
// RV32I: call zeroext i8 @__atomic_load_1
// RV32I: call void @__atomic_store_1
// RV32I: call zeroext i8 @__atomic_fetch_add_1
// RV32IA: load atomic i8, i8* %a seq_cst, align 1
// RV32IA: store atomic i8 %b, i8* %a seq_cst, align 1
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
2021-02-12 06:33:43 +08:00
// RV32IA: atomicrmw add i8* %a, i8 %b seq_cst, align 1
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
// RV64I: call zeroext i8 @__atomic_load_1
// RV64I: call void @__atomic_store_1
// RV64I: call zeroext i8 @__atomic_fetch_add_1
// RV64IA: load atomic i8, i8* %a seq_cst, align 1
// RV64IA: store atomic i8 %b, i8* %a seq_cst, align 1
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
2021-02-12 06:33:43 +08:00
// RV64IA: atomicrmw add i8* %a, i8 %b seq_cst, align 1
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
__c11_atomic_load(a, memory_order_seq_cst);
__c11_atomic_store(a, b, memory_order_seq_cst);
__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
}
void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) {
// RV32I: call i32 @__atomic_load_4
// RV32I: call void @__atomic_store_4
// RV32I: call i32 @__atomic_fetch_add_4
// RV32IA: load atomic i32, i32* %a seq_cst, align 4
// RV32IA: store atomic i32 %b, i32* %a seq_cst, align 4
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
2021-02-12 06:33:43 +08:00
// RV32IA: atomicrmw add i32* %a, i32 %b seq_cst, align 4
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
// RV64I: call signext i32 @__atomic_load_4
// RV64I: call void @__atomic_store_4
// RV64I: call signext i32 @__atomic_fetch_add_4
// RV64IA: load atomic i32, i32* %a seq_cst, align 4
// RV64IA: store atomic i32 %b, i32* %a seq_cst, align 4
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
2021-02-12 06:33:43 +08:00
// RV64IA: atomicrmw add i32* %a, i32 %b seq_cst, align 4
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
__c11_atomic_load(a, memory_order_seq_cst);
__c11_atomic_store(a, b, memory_order_seq_cst);
__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
}
void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) {
// RV32I: call i64 @__atomic_load_8
// RV32I: call void @__atomic_store_8
// RV32I: call i64 @__atomic_fetch_add_8
// RV32IA: call i64 @__atomic_load_8
// RV32IA: call void @__atomic_store_8
// RV32IA: call i64 @__atomic_fetch_add_8
// RV64I: call i64 @__atomic_load_8
// RV64I: call void @__atomic_store_8
// RV64I: call i64 @__atomic_fetch_add_8
// RV64IA: load atomic i64, i64* %a seq_cst, align 8
// RV64IA: store atomic i64 %b, i64* %a seq_cst, align 8
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. The ability to specify alignment was recently added, and it's an important property which we should ensure is set as expected by Clang. (Especially before making further changes to Clang's code in this area.) But, because it's on the end of the lines, the existing tests all ignore it. Therefore, update all the tests to also verify the expected alignment for atomicrmw and cmpxchg. While I was in there, I also updated uses of 'load atomic' and 'store atomic', and added the memory ordering, where that was missing.
2021-02-12 06:33:43 +08:00
// RV64IA: atomicrmw add i64* %a, i64 %b seq_cst, align 8
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
2019-08-27 23:41:16 +08:00
__c11_atomic_load(a, memory_order_seq_cst);
__c11_atomic_store(a, b, memory_order_seq_cst);
__c11_atomic_fetch_add(a, b, memory_order_seq_cst);
}