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llvm-project/llvm/test/CodeGen/AArch64/no-quad-ldp-stp.ll

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[AArch64] Rename 'no-quad-ldst-pairs' to 'slow-paired-128' In order to follow the pattern of the existing 'slow-misaligned-128store' option, rename the option 'no-quad-ldst-pairs' to 'slow-paired-128'. llvm-svn: 292954
2017-01-25 01:34:31 +08:00
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 -verify-machineinstrs -asm-verbose=false | FileCheck %s
[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
2016-07-19 21:35:11 +08:00
; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
[AArch64] Disable LDP/STP for quads Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
2016-04-14 02:31:45 +08:00
[AArch64] Switch regression tests to test features not CPUs Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 llvm-svn: 273271
2016-06-21 23:16:34 +08:00
; CHECK-LABEL: test_nopair_st
[AArch64] Disable LDP/STP for quads Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
2016-04-14 02:31:45 +08:00
; CHECK: str
; CHECK: stur
; CHECK-NOT: stp
[AArch64] Switch regression tests to test features not CPUs Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 llvm-svn: 273271
2016-06-21 23:16:34 +08:00
define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
[AArch64] Disable LDP/STP for quads Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
2016-04-14 02:31:45 +08:00
%tmp1 = bitcast double* %ptr to <2 x double>*
store <2 x double> %v2, <2 x double>* %tmp1, align 16
%add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
%tmp = bitcast double* %add.ptr to <2 x double>*
store <2 x double> %v1, <2 x double>* %tmp, align 16
ret void
}
[AArch64] Switch regression tests to test features not CPUs Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 llvm-svn: 273271
2016-06-21 23:16:34 +08:00
; CHECK-LABEL: test_nopair_ld
[AArch64] Disable LDP/STP for quads Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
2016-04-14 02:31:45 +08:00
; CHECK: ldr
; CHECK: ldr
; CHECK-NOT: ldp
[AArch64] Switch regression tests to test features not CPUs Summary: We have switched to using features for all heuristics, but the tests for these are still using -mcpu, which means we are not directly testing the features. This converts at least some of the existing regression tests to use the new features. This still leaves the following features untested: merge-narrow-ld predictable-select-expensive alternate-sextload-cvt-f32-pattern disable-latency-sched-heuristic Reviewers: mcrosier, t.p.northover, rengolin Subscribers: MatzeB, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21288 llvm-svn: 273271
2016-06-21 23:16:34 +08:00
define <2 x i64> @test_nopair_ld(i64* %p) {
[AArch64] Disable LDP/STP for quads Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
2016-04-14 02:31:45 +08:00
%a1 = bitcast i64* %p to <2 x i64>*
%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
%add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
%a2 = bitcast i64* %add.ptr2 to <2 x i64>*
%tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
%add = add nsw <2 x i64> %tmp1, %tmp2
ret <2 x i64> %add
}