2014-03-25 00:07:25 +08:00
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//===-- R700Instructions.td - R700 Instruction defs -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TableGen definitions for instructions which are:
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// - Available to R700 and newer VLIW4/VLIW5 GPUs
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// - Available only on R700 family GPUs.
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//
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//===----------------------------------------------------------------------===//
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AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
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def isR700 : Predicate<"Subtarget->getGeneration() == R600Subtarget::R700">;
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2014-03-25 00:07:25 +08:00
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let Predicates = [isR700] in {
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def SIN_r700 : SIN_Common<0x6E>;
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def COS_r700 : COS_Common<0x6F>;
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}
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