2012-04-18 02:03:21 +08:00
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//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Mips Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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2012-07-10 02:46:47 +08:00
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#include "MipsRegisterInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "MipsSubtarget.h"
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2012-04-18 02:03:21 +08:00
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#include "llvm/MC/MCDisassembler.h"
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2012-08-15 03:06:05 +08:00
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#include "llvm/MC/MCFixedLenDisassembler.h"
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2012-04-18 02:03:21 +08:00
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#include "llvm/MC/MCInst.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/MC/MCSubtargetInfo.h"
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2012-04-18 02:03:21 +08:00
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#include "llvm/Support/MathExtras.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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2012-04-18 02:03:21 +08:00
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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2012-05-01 22:34:24 +08:00
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namespace {
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2012-07-10 02:46:47 +08:00
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/// MipsDisassemblerBase - a disasembler class for Mips.
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class MipsDisassemblerBase : public MCDisassembler {
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2012-04-18 02:03:21 +08:00
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public:
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/// Constructor - Initializes the disassembler.
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///
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2012-07-10 02:46:47 +08:00
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MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MCDisassembler(STI), RegInfo(Info),
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IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
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2012-04-18 02:03:21 +08:00
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2012-07-10 02:46:47 +08:00
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virtual ~MipsDisassemblerBase() {}
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2012-04-18 02:03:21 +08:00
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2013-08-04 06:16:16 +08:00
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const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
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2012-07-10 02:46:47 +08:00
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2013-08-28 08:55:15 +08:00
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bool isN64() const { return IsN64; }
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2012-04-18 02:03:21 +08:00
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private:
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OwningPtr<const MCRegisterInfo> RegInfo;
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bool IsN64;
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protected:
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2012-04-18 02:03:21 +08:00
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bool isBigEndian;
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};
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2012-07-10 02:46:47 +08:00
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/// MipsDisassembler - a disasembler class for Mips32.
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class MipsDisassembler : public MipsDisassemblerBase {
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bool IsMicroMips;
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2012-04-18 02:03:21 +08:00
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public:
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/// Constructor - Initializes the disassembler.
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///
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2012-07-10 02:46:47 +08:00
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MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Info, bigEndian) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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2012-04-18 02:03:21 +08:00
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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};
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2012-04-18 02:03:21 +08:00
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2012-07-10 02:46:47 +08:00
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/// Mips64Disassembler - a disasembler class for Mips64.
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class Mips64Disassembler : public MipsDisassemblerBase {
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public:
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/// Constructor - Initializes the disassembler.
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///
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Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Info, bigEndian) {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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2012-04-18 02:03:21 +08:00
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};
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2012-05-01 22:34:24 +08:00
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} // end anonymous namespace
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2012-04-18 02:03:21 +08:00
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// Forward declare these because the autogenerated code will reference them.
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// Definitions are further down.
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2013-08-07 07:08:38 +08:00
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-02-14 11:05:25 +08:00
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static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-08-07 07:08:38 +08:00
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-08-28 08:55:15 +08:00
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static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2013-08-14 08:53:38 +08:00
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2012-09-27 10:01:10 +08:00
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-08-21 06:58:56 +08:00
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-07-27 04:13:47 +08:00
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static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-08-09 05:54:26 +08:00
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static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-08-14 08:47:08 +08:00
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static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-04-18 08:52:44 +08:00
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2013-08-14 08:47:08 +08:00
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static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-04-18 08:52:44 +08:00
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2013-09-26 08:09:46 +08:00
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static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-09-26 07:50:44 +08:00
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static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2013-10-21 20:26:50 +08:00
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static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2013-11-04 22:53:22 +08:00
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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2013-10-30 00:38:59 +08:00
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// DecodeJumpTargetMM - Decode microMIPS jump target, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2013-10-21 21:07:13 +08:00
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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2013-09-06 20:30:36 +08:00
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2013-11-18 20:32:49 +08:00
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// Decode the immediate field of an LSA instruction which
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// is off by one.
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static DecodeStatus DecodeLSAImm(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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2012-04-18 02:03:21 +08:00
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static DecodeStatus DecodeInsSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeExtSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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namespace llvm {
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extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
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TheMips64elTarget;
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}
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static MCDisassembler *createMipsDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
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}
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static MCDisassembler *createMipselDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
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}
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static MCDisassembler *createMips64Disassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
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}
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static MCDisassembler *createMips64elDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
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}
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extern "C" void LLVMInitializeMipsDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
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createMipsDisassembler);
|
|
|
|
|
TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
|
|
|
|
|
createMipselDisassembler);
|
|
|
|
|
TargetRegistry::RegisterMCDisassembler(TheMips64Target,
|
|
|
|
|
createMips64Disassembler);
|
|
|
|
|
TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
|
|
|
|
|
createMips64elDisassembler);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2014-04-01 02:51:43 +08:00
|
|
|
#include "MipsGenDisassemblerTables.inc"
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205229
2014-04-01 01:43:46 +08:00
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
/// readInstruction - read four bytes from the MemoryObject
|
|
|
|
|
/// and return 32 bit word sorted according to the given endianess
|
|
|
|
|
static DecodeStatus readInstruction32(const MemoryObject ®ion,
|
|
|
|
|
uint64_t address,
|
|
|
|
|
uint64_t &size,
|
|
|
|
|
uint32_t &insn,
|
2013-09-06 20:30:36 +08:00
|
|
|
bool isBigEndian,
|
|
|
|
|
bool IsMicroMips) {
|
2012-04-18 02:03:21 +08:00
|
|
|
uint8_t Bytes[4];
|
|
|
|
|
|
|
|
|
|
// We want to read exactly 4 Bytes of data.
|
2013-05-24 18:54:58 +08:00
|
|
|
if (region.readBytes(address, 4, Bytes) == -1) {
|
2012-04-18 02:03:21 +08:00
|
|
|
size = 0;
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (isBigEndian) {
|
|
|
|
|
// Encoded as a big-endian 32-bit word in the stream.
|
|
|
|
|
insn = (Bytes[3] << 0) |
|
|
|
|
|
(Bytes[2] << 8) |
|
|
|
|
|
(Bytes[1] << 16) |
|
|
|
|
|
(Bytes[0] << 24);
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
// Encoded as a small-endian 32-bit word in the stream.
|
2013-09-06 20:30:36 +08:00
|
|
|
// Little-endian byte ordering:
|
|
|
|
|
// mips32r2: 4 | 3 | 2 | 1
|
|
|
|
|
// microMIPS: 2 | 1 | 4 | 3
|
|
|
|
|
if (IsMicroMips) {
|
|
|
|
|
insn = (Bytes[2] << 0) |
|
|
|
|
|
(Bytes[3] << 8) |
|
|
|
|
|
(Bytes[0] << 16) |
|
|
|
|
|
(Bytes[1] << 24);
|
|
|
|
|
} else {
|
|
|
|
|
insn = (Bytes[0] << 0) |
|
|
|
|
|
(Bytes[1] << 8) |
|
|
|
|
|
(Bytes[2] << 16) |
|
|
|
|
|
(Bytes[3] << 24);
|
|
|
|
|
}
|
2012-04-18 02:03:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DecodeStatus
|
|
|
|
|
MipsDisassembler::getInstruction(MCInst &instr,
|
|
|
|
|
uint64_t &Size,
|
|
|
|
|
const MemoryObject &Region,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
raw_ostream &vStream,
|
|
|
|
|
raw_ostream &cStream) const {
|
|
|
|
|
uint32_t Insn;
|
|
|
|
|
|
|
|
|
|
DecodeStatus Result = readInstruction32(Region, Address, Size,
|
2013-09-06 20:30:36 +08:00
|
|
|
Insn, isBigEndian, IsMicroMips);
|
2012-04-18 02:03:21 +08:00
|
|
|
if (Result == MCDisassembler::Fail)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2013-09-06 20:30:36 +08:00
|
|
|
if (IsMicroMips) {
|
|
|
|
|
// Calling the auto-generated decoder function.
|
|
|
|
|
Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
|
|
|
|
|
this, STI);
|
|
|
|
|
if (Result != MCDisassembler::Fail) {
|
|
|
|
|
Size = 4;
|
|
|
|
|
return Result;
|
|
|
|
|
}
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
// Calling the auto-generated decoder function.
|
2012-08-15 03:06:05 +08:00
|
|
|
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
|
|
|
|
|
this, STI);
|
2012-04-18 02:03:21 +08:00
|
|
|
if (Result != MCDisassembler::Fail) {
|
|
|
|
|
Size = 4;
|
|
|
|
|
return Result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DecodeStatus
|
|
|
|
|
Mips64Disassembler::getInstruction(MCInst &instr,
|
|
|
|
|
uint64_t &Size,
|
|
|
|
|
const MemoryObject &Region,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
raw_ostream &vStream,
|
|
|
|
|
raw_ostream &cStream) const {
|
|
|
|
|
uint32_t Insn;
|
|
|
|
|
|
|
|
|
|
DecodeStatus Result = readInstruction32(Region, Address, Size,
|
2013-09-06 20:30:36 +08:00
|
|
|
Insn, isBigEndian, false);
|
2012-04-18 02:03:21 +08:00
|
|
|
if (Result == MCDisassembler::Fail)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
// Calling the auto-generated decoder function.
|
2012-08-15 03:06:05 +08:00
|
|
|
Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
|
|
|
|
|
this, STI);
|
2012-04-18 02:03:21 +08:00
|
|
|
if (Result != MCDisassembler::Fail) {
|
|
|
|
|
Size = 4;
|
|
|
|
|
return Result;
|
|
|
|
|
}
|
|
|
|
|
// If we fail to decode in Mips64 decoder space we can try in Mips32
|
2012-08-15 03:06:05 +08:00
|
|
|
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
|
|
|
|
|
this, STI);
|
2012-04-18 02:03:21 +08:00
|
|
|
if (Result != MCDisassembler::Fail) {
|
|
|
|
|
Size = 4;
|
|
|
|
|
return Result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
|
|
|
|
|
const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
|
|
|
|
|
return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
|
|
|
|
|
}
|
|
|
|
|
|
2013-02-14 11:05:25 +08:00
|
|
|
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2012-04-18 02:03:21 +08:00
|
|
|
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
|
2012-07-10 02:46:47 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2012-04-18 02:03:21 +08:00
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
2013-08-07 07:08:38 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
|
2012-07-10 02:46:47 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-28 08:55:15 +08:00
|
|
|
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
|
|
|
|
|
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
|
|
|
|
|
|
|
|
|
|
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 08:53:38 +08:00
|
|
|
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2013-08-07 07:08:38 +08:00
|
|
|
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
2012-09-27 10:01:10 +08:00
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-21 06:58:56 +08:00
|
|
|
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2013-06-27 06:23:32 +08:00
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-27 04:13:47 +08:00
|
|
|
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 7)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeMem(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
2012-08-15 03:06:05 +08:00
|
|
|
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
|
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
2012-07-10 02:46:47 +08:00
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
|
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
2012-04-18 02:03:21 +08:00
|
|
|
|
|
|
|
|
if(Inst.getOpcode() == Mips::SC){
|
2012-07-10 02:46:47 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
}
|
|
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
2012-04-18 02:03:21 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-10-21 21:07:13 +08:00
|
|
|
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
|
|
|
|
|
uint64_t Address, const void *Decoder) {
|
|
|
|
|
int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
|
|
|
|
|
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
|
|
|
|
|
unsigned Base = fieldFromInstruction(Insn, 11, 5);
|
|
|
|
|
|
|
|
|
|
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
|
|
|
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
|
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
2013-12-05 19:06:22 +08:00
|
|
|
|
|
|
|
|
// The immediate field of an LD/ST instruction is scaled which means it must
|
|
|
|
|
// be multiplied (when decoding) by the size (in bytes) of the instructions'
|
|
|
|
|
// data format.
|
|
|
|
|
// .b - 1 byte
|
|
|
|
|
// .h - 2 bytes
|
|
|
|
|
// .w - 4 bytes
|
|
|
|
|
// .d - 8 bytes
|
|
|
|
|
switch(Inst.getOpcode())
|
|
|
|
|
{
|
|
|
|
|
default:
|
|
|
|
|
assert (0 && "Unexpected instruction");
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
break;
|
|
|
|
|
case Mips::LD_B:
|
|
|
|
|
case Mips::ST_B:
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
|
break;
|
|
|
|
|
case Mips::LD_H:
|
|
|
|
|
case Mips::ST_H:
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 1));
|
|
|
|
|
break;
|
|
|
|
|
case Mips::LD_W:
|
|
|
|
|
case Mips::ST_W:
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 2));
|
|
|
|
|
break;
|
|
|
|
|
case Mips::LD_D:
|
|
|
|
|
case Mips::ST_D:
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 3));
|
|
|
|
|
break;
|
|
|
|
|
}
|
2013-10-21 21:07:13 +08:00
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-06 20:30:36 +08:00
|
|
|
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
int Offset = SignExtend32<12>(Insn & 0x0fff);
|
|
|
|
|
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
|
|
|
|
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
|
|
|
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
|
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
|
|
2014-03-01 02:22:56 +08:00
|
|
|
if (Inst.getOpcode() == Mips::SC_MM)
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
|
2013-09-06 20:30:36 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
|
|
|
|
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
|
|
|
|
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
|
|
|
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
|
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
|
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeFMem(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
2012-08-15 03:06:05 +08:00
|
|
|
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
|
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
2012-04-18 02:03:21 +08:00
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
|
2013-08-07 07:08:38 +08:00
|
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
2012-07-10 02:46:47 +08:00
|
|
|
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
2012-04-18 02:03:21 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
|
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
// Currently only hardware register 29 is supported.
|
|
|
|
|
if (RegNo != 29)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2012-07-10 02:46:47 +08:00
|
|
|
if (RegNo > 30 || RegNo %2)
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2012-07-10 02:46:47 +08:00
|
|
|
;
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
2012-04-18 02:03:21 +08:00
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-09 05:54:26 +08:00
|
|
|
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2012-09-27 10:01:10 +08:00
|
|
|
if (RegNo >= 4)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2013-08-09 05:54:26 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
|
2012-09-27 10:01:10 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 08:47:08 +08:00
|
|
|
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2013-04-18 08:52:44 +08:00
|
|
|
if (RegNo >= 4)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2013-08-14 08:47:08 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
|
2013-04-18 08:52:44 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 08:47:08 +08:00
|
|
|
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
2013-04-18 08:52:44 +08:00
|
|
|
if (RegNo >= 4)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
2013-08-14 08:47:08 +08:00
|
|
|
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
|
2013-04-18 08:52:44 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-26 08:09:46 +08:00
|
|
|
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-26 07:50:44 +08:00
|
|
|
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 31)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-10-21 20:26:50 +08:00
|
|
|
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
|
|
|
|
|
unsigned RegNo,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
if (RegNo > 7)
|
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
|
|
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
|
|
|
|
|
unsigned Offset,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
unsigned BranchOffset = Offset & 0xffff;
|
|
|
|
|
BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
|
2012-08-15 03:06:05 +08:00
|
|
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
|
2012-04-18 02:03:21 +08:00
|
|
|
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-11-04 22:53:22 +08:00
|
|
|
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
|
|
|
|
|
unsigned Offset,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
unsigned BranchOffset = Offset & 0xffff;
|
|
|
|
|
BranchOffset = SignExtend32<18>(BranchOffset << 1);
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-10-30 00:38:59 +08:00
|
|
|
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
2012-04-18 02:03:21 +08:00
|
|
|
|
|
|
|
|
static DecodeStatus DecodeSimm16(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2013-11-18 20:32:49 +08:00
|
|
|
static DecodeStatus DecodeLSAImm(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
// We add one to the immediate field as it was encoded as 'imm - 1'.
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(Insn + 1));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 02:03:21 +08:00
|
|
|
static DecodeStatus DecodeInsSize(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
// First we need to grab the pos(lsb) from MCInst.
|
|
|
|
|
int Pos = Inst.getOperand(2).getImm();
|
|
|
|
|
int Size = (int) Insn - Pos + 1;
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DecodeStatus DecodeExtSize(MCInst &Inst,
|
|
|
|
|
unsigned Insn,
|
|
|
|
|
uint64_t Address,
|
|
|
|
|
const void *Decoder) {
|
|
|
|
|
int Size = (int) Insn + 1;
|
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
|
|
|
return MCDisassembler::Success;
|
|
|
|
|
}
|