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llvm-project/llvm/lib/Target/AMDGPU/Processors.td

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R600: Clean up comments in Processors.td llvm-svn: 181032
2013-05-04 01:21:14 +08:00
//===-- Processors.td - R600 Processor definitions ------------------------===//
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
2012-12-12 05:25:42 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
: Processor<Name, itin, Features>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// R600
//===----------------------------------------------------------------------===//
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
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def : Proc<"", R600_VLIW5_Itin,
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
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[FeatureR600, FeatureVertexCache]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
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def : Proc<"r600", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>;
def : Proc<"r630", R600_VLIW5_Itin,
[FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"rs880", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR600, FeatureWavefrontSize16]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"rv670", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// R700
//===----------------------------------------------------------------------===//
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"rv710", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"rv730", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"rv770", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// Evergreen
//===----------------------------------------------------------------------===//
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"cedar", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"redwood", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"sumo", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"juniper", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"cypress", R600_VLIW5_Itin,
R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
2014-01-23 05:55:40 +08:00
[FeatureEvergreen, FeatureFP64, FeatureVertexCache,
FeatureWavefrontSize64]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// Northern Islands
//===----------------------------------------------------------------------===//
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"barts", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"turks", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"caicos", R600_VLIW5_Itin,
R600: Recommit 199842: Add work-around for the CF stack entry HW bug The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
2014-01-24 00:18:02 +08:00
[FeatureNorthernIslands, FeatureCFALUBug]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips llvm-svn: 180759
2013-04-30 08:14:17 +08:00
def : Proc<"cayman", R600_VLIW4_Itin,
R600: Rework subtarget info and remove AMDILDevice classes This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
2013-06-08 04:37:48 +08:00
[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
R600: Fix the fetch limits for R600 generation GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
2013-06-08 04:28:55 +08:00
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// Southern Islands
//===----------------------------------------------------------------------===//
R600/SI: Add subtarget feature for if f32 fma is fast llvm-svn: 227483
2015-01-30 03:34:25 +08:00
def : ProcessorModel<"SI", SIFullSpeedModel,
[FeatureSouthernIslands, FeatureFastFMAF32]
>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Add subtarget feature for if f32 fma is fast llvm-svn: 227483
2015-01-30 03:34:25 +08:00
def : ProcessorModel<"tahiti", SIFullSpeedModel,
[FeatureSouthernIslands, FeatureFastFMAF32]
>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
2015-01-14 09:13:19 +08:00
def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
2015-01-14 09:13:19 +08:00
def : ProcessorModel<"verde", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
2015-01-14 09:13:19 +08:00
def : ProcessorModel<"oland", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
2015-01-14 09:13:19 +08:00
def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
//===----------------------------------------------------------------------===//
// Sea Islands
//===----------------------------------------------------------------------===//
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
def : ProcessorModel<"bonaire", SIQuarterSpeedModel,
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
[FeatureSeaIslands, FeatureLDSBankCount32, FeatureISAVersion7_0_0]
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
def : ProcessorModel<"kabini", SIQuarterSpeedModel,
[FeatureSeaIslands, FeatureLDSBankCount16]
>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
def : ProcessorModel<"kaveri", SIQuarterSpeedModel,
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
[FeatureSeaIslands, FeatureLDSBankCount32, FeatureISAVersion7_0_0]
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
>;
R600: Re-format Processors.td This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
2013-12-12 01:51:51 +08:00
R600/SI: Add subtarget feature for if f32 fma is fast llvm-svn: 227483
2015-01-30 03:34:25 +08:00
def : ProcessorModel<"hawaii", SIFullSpeedModel,
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
[FeatureSeaIslands, FeatureFastFMAF32, FeatureLDSBankCount32,
FeatureISAVersion7_0_1]
R600/SI: Add subtarget feature for if f32 fma is fast llvm-svn: 227483
2015-01-30 03:34:25 +08:00
>;
R600/SI: Add processor type for Mullins. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 207846
2014-05-02 23:41:49 +08:00
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
2015-05-26 00:15:54 +08:00
def : ProcessorModel<"mullins", SIQuarterSpeedModel,
[FeatureSeaIslands, FeatureLDSBankCount16]>;
R600/SI: Add VI instructions llvm-svn: 223603
2014-12-07 20:18:57 +08:00
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
2015-01-14 09:13:19 +08:00
//===----------------------------------------------------------------------===//
// Volcanic Islands
//===----------------------------------------------------------------------===//
R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. llvm-svn: 231659
2015-03-09 23:48:09 +08:00
def : ProcessorModel<"tonga", SIQuarterSpeedModel,
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
[FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0]
R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. llvm-svn: 231659
2015-03-09 23:48:09 +08:00
>;
R600/SI: Add VI instructions llvm-svn: 223603
2014-12-07 20:18:57 +08:00
R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. llvm-svn: 231659
2015-03-09 23:48:09 +08:00
def : ProcessorModel<"iceland", SIQuarterSpeedModel,
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
[FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0]
R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. llvm-svn: 231659
2015-03-09 23:48:09 +08:00
>;
R600/SI: Add VI instructions llvm-svn: 223603
2014-12-07 20:18:57 +08:00
AMDGPU/SI: Add hsa code object directives Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
2015-06-27 05:15:07 +08:00
def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureISAVersion8_0_1]
>;
AMDGPU/SI: Add Fiji support Patch by: Alex Deucher llvm-svn: 244255
2015-08-07 03:43:02 +08:00
def : ProcessorModel<"fiji", SIQuarterSpeedModel,
[FeatureVolcanicIslands, FeatureISAVersion8_0_1]
>;