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llvm-project/llvm/test/MC/ARM/thumb-diagnostics.s

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Add testcase for r137746. llvm-svn: 137754
2011-08-17 05:11:21 +08:00
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
Thumb assembly parsing and encoding for MOV. llvm-svn: 138076
2011-08-20 04:46:54 +08:00
@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
Add testcase for r137746. llvm-svn: 137754
2011-08-17 05:11:21 +08:00
@ Check for various assembly diagnostic messages on invalid input.
@ ADD instruction w/o 'S' suffix.
add r1, r2, r3
@ CHECK-ERRORS: error: invalid instruction
@ CHECK-ERRORS: add r1, r2, r3
@ CHECK-ERRORS: ^
Thumb parsing diagnostics for low-reg requirements on ADD and MOV. llvm-svn: 137779
2011-08-17 06:20:01 +08:00
@ Instructions which require v6+ for both registers to be low regs.
add r2, r3
mov r2, r3
@ CHECK-ERRORS: error: instruction variant requires Thumb2
@ CHECK-ERRORS: add r2, r3
@ CHECK-ERRORS: ^
Thumb assembly parsing and encoding for MOV. llvm-svn: 138076
2011-08-20 04:46:54 +08:00
@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
@ CHECK-ERRORS-V5: mov r2, r3
@ CHECK-ERRORS-V5: ^
Thumb assembly parsing and encoding for ASR. llvm-svn: 137889
2011-08-18 06:49:09 +08:00
@ Out of range immediates for ASR instruction.
asrs r2, r3, #33
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: asrs r2, r3, #33
@ CHECK-ERRORS: ^
ARM assembly parsing and encoding test for BKPT. llvm-svn: 137898
2011-08-18 07:11:13 +08:00
@ Out of range immediates for BKPT instruction.
bkpt #256
bkpt #-1
error: invalid operand for instruction
bkpt #256
^
error: invalid operand for instruction
bkpt #-1
^
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-19 05:50:53 +08:00
@ Invalid writeback and register lists for LDM
ldm r2!, {r5, r8}
ldm r2, {r5, r7}
Thumb assemmbly parsing diagnostic improvements for LDM. llvm-svn: 138287
2011-08-23 07:01:07 +08:00
ldm r2!, {r2, r3, r4}
Thumb assembly parsing and encoding for LDM instruction. Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
2011-08-19 05:50:53 +08:00
@ CHECK-ERRORS: error: registers must be in range r0-r7
@ CHECK-ERRORS: ldm r2!, {r5, r8}
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: writeback operator '!' expected
@ CHECK-ERRORS: ldm r2, {r5, r7}
@ CHECK-ERRORS: ^
Thumb assemmbly parsing diagnostic improvements for LDM. llvm-svn: 138287
2011-08-23 07:01:07 +08:00
@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
Fix think-o. llvm-svn: 138288
2011-08-23 07:04:26 +08:00
@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}
Thumb assemmbly parsing diagnostic improvements for LDM. llvm-svn: 138287
2011-08-23 07:01:07 +08:00
@ CHECK-ERRORS: ^
Thumb assembly parsing and encoding for LSL(immediate). llvm-svn: 138063
2011-08-20 03:29:25 +08:00
Improve error checking for tPUSH and tPOP register lists. llvm-svn: 138295
2011-08-23 07:17:34 +08:00
@ Invalid writeback and register lists for PUSH/POP
pop {r1, r2, r10}
push {r8, r9}
@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
@ CHECK-ERRORS: pop {r1, r2, r10}
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
@ CHECK-ERRORS: push {r8, r9}
@ CHECK-ERRORS: ^
Thumb parsing and encoding for STM. llvm-svn: 138345
2011-08-24 02:15:37 +08:00
@ Invalid writeback and register lists for STM
stm r1, {r2, r6}
stm r1!, {r2, r9}
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding for STM. llvm-svn: 138345
2011-08-24 02:15:37 +08:00
@ CHECK-ERRORS: stm r1, {r2, r6}
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: registers must be in range r0-r7
@ CHECK-ERRORS: stm r1!, {r2, r9}
@ CHECK-ERRORS: ^
Improve error checking for tPUSH and tPOP register lists. llvm-svn: 138295
2011-08-23 07:17:34 +08:00
Thumb assembly parsing and encoding for LSL(immediate). llvm-svn: 138063
2011-08-20 03:29:25 +08:00
@ Out of range immediates for LSL instruction.
lsls r4, r5, #-1
lsls r4, r5, #32
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: lsls r4, r5, #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: lsls r4, r5, #32
@ CHECK-ERRORS: ^
Thumb assembly parsing and encoding for MUL. llvm-svn: 138108
2011-08-20 06:07:46 +08:00
@ Mismatched source/destination operands for MUL instruction.
muls r1, r2, r3
Be more lenient on tied operand matching for MUL. llvm-svn: 138124
2011-08-20 06:30:46 +08:00
@ CHECK-ERRORS: error: destination register must match source register
Thumb assembly parsing and encoding for MUL. llvm-svn: 138108
2011-08-20 06:07:46 +08:00
@ CHECK-ERRORS: muls r1, r2, r3
@ CHECK-ERRORS: ^
Thumb parsing and encoding for STR. Not including tSTRspi. llvm-svn: 138347
2011-08-24 02:33:38 +08:00
@ Out of range immediates for STR instruction.
str r2, [r7, #-1]
str r5, [r1, #3]
str r3, [r7, #128]
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding for STR. Not including tSTRspi. llvm-svn: 138347
2011-08-24 02:33:38 +08:00
@ CHECK-ERRORS: str r2, [r7, #-1]
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding for STR. Not including tSTRspi. llvm-svn: 138347
2011-08-24 02:33:38 +08:00
@ CHECK-ERRORS: str r5, [r1, #3]
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding for STR. Not including tSTRspi. llvm-svn: 138347
2011-08-24 02:33:38 +08:00
@ CHECK-ERRORS: str r3, [r7, #128]
@ CHECK-ERRORS: ^
Thumb parsing and encoding for SVC. llvm-svn: 138360
2011-08-24 03:49:10 +08:00
@ Out of range immediate for SVC instruction.
svc #-1
svc #256
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: svc #-1
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: arm-mode
Thumb parsing and encoding for SVC. llvm-svn: 138360
2011-08-24 03:49:10 +08:00
@ CHECK-ERRORS: svc #256
@ CHECK-ERRORS: ^
Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
2011-08-25 05:22:15 +08:00
@ Out of range immediate for ADD SP instructions
add sp, #-1
add sp, #3
add sp, sp, #512
add r2, sp, #1024
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
2011-08-25 05:22:15 +08:00
@ CHECK-ERRORS: add sp, #-1
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
2011-08-25 05:22:15 +08:00
@ CHECK-ERRORS: add sp, #3
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: thumb2
Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
2011-08-25 05:22:15 +08:00
@ CHECK-ERRORS: add sp, sp, #512
@ CHECK-ERRORS: ^
ARM: improved assembler diagnostics for missing CPU features. When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
2012-04-25 06:40:08 +08:00
@ CHECK-ERRORS: error: instruction requires: arm-mode
Thumb parsing and encoding support for ADD SP instructions. Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
2011-08-25 05:22:15 +08:00
@ CHECK-ERRORS: add r2, sp, #1024
Thumb2 assembly parsing and encoding for ADD(immediate). llvm-svn: 138922
2011-09-01 08:28:52 +08:00
@ CHECK-ERRORS: ^
ARM: Thumb add(sp plus register) asm constraints. Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
2012-04-28 07:51:36 +08:00
add r2, sp, ip
@ CHECK-ERRORS: error: source register must be the same as destination
@ CHECK-ERRORS: add r2, sp, ip
@ CHECK-ERRORS: ^
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. llvm-svn: 155983
2012-05-02 17:43:18 +08:00
@------------------------------------------------------------------------------
@ WFE/WFI/YIELD - are not supported pre v6T2
@------------------------------------------------------------------------------
wfe
wfi
yield
@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: wfe
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: wfi
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: yield
@ CHECK-ERRORS: ^