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llvm-project/llvm/test/MC/ARM/mode-switch.s

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Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
@ Test ARM / Thumb mode switching with .code
Tidy up formatting. llvm-svn: 137747
2011-08-17 04:55:41 +08:00
@ RUN: llvm-mc -triple armv7-unknown-unknown -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding <%s | FileCheck %s
Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
.code 16
add.w r0, r0, r1
Tweak ADDrr fix. Bad check for explicit .w llvm-svn: 145863
2011-12-06 06:27:04 +08:00
@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00]
Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
.code 32
add r0, r0, r1
Tidy up formatting. llvm-svn: 137747
2011-08-17 04:55:41 +08:00
@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
Add support for ARM / Thumb mode switching with .code 16 and .code 32. llvm-svn: 134760
2011-07-09 06:36:29 +08:00
.code 16
ARM thumb assembly parsing for arithmetic flag setting instructions. Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. llvm-svn: 137746
2011-08-17 04:45:50 +08:00
adds r0, r0, r1
Tidy up formatting. llvm-svn: 137747
2011-08-17 04:55:41 +08:00
@ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]
ARM support the .arm and .thumb directives for assembly mode switching. llvm-svn: 146042
2011-12-08 02:04:19 +08:00
.arm
add r0, r0, r1
@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0]
.thumb
add.w r0, r0, r1
adds r0, r0, r1
@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00]
@ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18]