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llvm-project/llvm/test/CodeGen/AVR/shift.ll

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[AVR] Add a test for 64-bit left shifts llvm-svn: 289936
2016-12-16 19:40:00 +08:00
; RUN: llc < %s -march=avr | FileCheck %s
[AVR] Improve inline rotate/shift expansions These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
2020-08-23 20:17:29 +08:00
; Optimize for speed.
; CHECK-LABEL: shift_i8_i8_speed
define i8 @shift_i8_i8_speed(i8 %a, i8 %b) {
; CHECK: dec r22
; CHECK-NEXT: brmi .LBB0_2
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: lsl r24
; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB0_1
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%result = shl i8 %a, %b
ret i8 %result
}
; Optimize for size (producing slightly smaller code).
; CHECK-LABEL: shift_i8_i8_size
define i8 @shift_i8_i8_size(i8 %a, i8 %b) optsize {
; CHECK: .LBB1_1:
; CHECK-NEXT: dec r22
; CHECK-NEXT: brmi .LBB1_3
; CHECK: lsl r24
; CHECK-NEXT: rjmp .LBB1_1
; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: ret
%result = shl i8 %a, %b
ret i8 %result
}
; CHECK-LABEL: shift_i16_i16
define i16 @shift_i16_i16(i16 %a, i16 %b) {
; CHECK: dec r22
; CHECK-NEXT: brmi .LBB2_2
; CHECK-NEXT: .LBB2_1:
; CHECK-NEXT: lsl r24
; CHECK-NEXT: rol r25
; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB2_1
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ret
%result = shl i16 %a, %b
ret i16 %result
}
[AVR] Add a test for 64-bit left shifts llvm-svn: 289936
2016-12-16 19:40:00 +08:00
; CHECK-LABEL: shift_i64_i64
define i64 @shift_i64_i64(i64 %a, i64 %b) {
; CHECK: call __ashldi3
%result = shl i64 %a, %b
ret i64 %result
}
[AVR] Optimize 8-bit logic left/right shifts Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D89047
2021-01-23 23:54:16 +08:00
define i8 @lsl_i8_1(i8 %a) {
; CHECK-LABEL: lsl_i8_1:
; CHECK: lsl r24
%res = shl i8 %a, 1
ret i8 %res
}
define i8 @lsl_i8_2(i8 %a) {
; CHECK-LABEL: lsl_i8_2:
; CHECK: lsl r24
; CHECK-NEXT: lsl r24
%res = shl i8 %a, 2
ret i8 %res
}
define i8 @lsl_i8_3(i8 %a) {
; CHECK-LABEL: lsl_i8_3:
; CHECK: lsl r24
; CHECK-NEXT: lsl r24
; CHECK-NEXT: lsl r24
%res = shl i8 %a, 3
ret i8 %res
}
define i8 @lsl_i8_4(i8 %a) {
; CHECK-LABEL: lsl_i8_4:
; CHECK: swap r24
; CHECK-NEXT: andi r24, -16
%res = shl i8 %a, 4
ret i8 %res
}
define i8 @lsl_i8_5(i8 %a) {
; CHECK-LABEL: lsl_i8_5:
; CHECK: swap r24
; CHECK-NEXT: andi r24, -16
; CHECK-NEXT: lsl r24
%res = shl i8 %a, 5
ret i8 %res
}
define i8 @lsl_i8_6(i8 %a) {
; CHECK-LABEL: lsl_i8_6:
; CHECK: swap r24
; CHECK-NEXT: andi r24, -16
; CHECK-NEXT: lsl r24
; CHECK-NEXT: lsl r24
%res = shl i8 %a, 6
ret i8 %res
}
define i8 @lsr_i8_1(i8 %a) {
; CHECK-LABEL: lsr_i8_1:
; CHECK: lsr r24
%res = lshr i8 %a, 1
ret i8 %res
}
define i8 @lsr_i8_2(i8 %a) {
; CHECK-LABEL: lsr_i8_2:
; CHECK: lsr r24
; CHECK-NEXT: lsr r24
%res = lshr i8 %a, 2
ret i8 %res
}
define i8 @lsr_i8_3(i8 %a) {
; CHECK-LABEL: lsr_i8_3:
; CHECK: lsr r24
; CHECK-NEXT: lsr r24
; CHECK-NEXT: lsr r24
%res = lshr i8 %a, 3
ret i8 %res
}
define i8 @lsr_i8_4(i8 %a) {
; CHECK-LABEL: lsr_i8_4:
; CHECK: swap r24
; CHECK-NEXT: andi r24, 15
%res = lshr i8 %a, 4
ret i8 %res
}
define i8 @lsr_i8_5(i8 %a) {
; CHECK-LABEL: lsr_i8_5:
; CHECK: swap r24
; CHECK-NEXT: andi r24, 15
; CHECK-NEXT: lsr r24
%res = lshr i8 %a, 5
ret i8 %res
}
define i8 @lsr_i8_6(i8 %a) {
; CHECK-LABEL: lsr_i8_6:
; CHECK: swap r24
; CHECK-NEXT: andi r24, 15
; CHECK-NEXT: lsr r24
; CHECK-NEXT: lsr r24
%res = lshr i8 %a, 6
ret i8 %res
}
[AVR] Optimize 8-bit int shift Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D90678
2021-01-24 11:04:37 +08:00
define i8 @lsl_i8_7(i8 %a) {
; CHECK-LABEL: lsl_i8_7
; CHECK: ror r24
; CHECK-NEXT: clr r24
; CHECK-NEXT: ror r24
%result = shl i8 %a, 7
ret i8 %result
}
define i8 @lsr_i8_7(i8 %a) {
; CHECK-LABEL: lsr_i8_7
; CHECK: rol r24
; CHECK-NEXT: clr r24
; CHECK-NEXT: rol r24
%result = lshr i8 %a, 7
ret i8 %result
}
define i8 @asr_i8_7(i8 %a) {
; CHECK-LABEL: asr_i8_7
; CHECK: lsl r24
; CHECK-NEXT: sbc r24, r24
%result = ashr i8 %a, 7
ret i8 %result
}